Paper
6 November 2019 Computationally efficient index generation unit using a Bloom filter
Author Affiliations +
Proceedings Volume 11176, Photonics Applications in Astronomy, Communications, Industry, and High-Energy Physics Experiments 2019; 111761L (2019) https://doi.org/10.1117/12.2534641
Event: Photonics Applications in Astronomy, Communications, Industry, and High-Energy Physics Experiments 2019, 2019, Wilga, Poland
Abstract
Efficient implementation of index generation functions is attracting significant interest due to the dynamic development of technologies such as Big Data and Internet of Things. These functions can be realized using a circuit called index generation unit. However, the better linear transformation of an index generation function is found, the larger auxiliary memory is used. Lately, the architecture that uses probabilistic data structure was proposed. However, it requires several independent hash functions. Selecting proper hash functions is a complex issue. Thus, in this paper we analyse a structure that uses single hash function, i.e. One-Hashing Bloom Filter. It requires additional modulo stage to compute several independent hashes. However, the obtained results prove that additional computations, can be easily implemented in FPGA devices.
© (2019) COPYRIGHT Society of Photo-Optical Instrumentation Engineers (SPIE). Downloading of the abstract is permitted for personal use only.
Tomasz Mazurkiewicz "Computationally efficient index generation unit using a Bloom filter", Proc. SPIE 11176, Photonics Applications in Astronomy, Communications, Industry, and High-Energy Physics Experiments 2019, 111761L (6 November 2019); https://doi.org/10.1117/12.2534641
Advertisement
Advertisement
RIGHTS & PERMISSIONS
Get copyright permission  Get copyright permission on Copyright Marketplace
KEYWORDS
Logic

Field programmable gate arrays

Binary data

Multiplexers

Content addressable memory

Programmable logic devices

RELATED CONTENT

Faster and smaller hardware implementation of XTR
Proceedings of SPIE (August 25 2006)
A design of online scheme for evaluation of multinomials
Proceedings of SPIE (September 16 2005)
A VLSI architecture for high performance CABAC encoding
Proceedings of SPIE (June 24 2005)
Arithmetic processor design for the T9000 transputer
Proceedings of SPIE (December 01 1991)
A decimal carry-free adder
Proceedings of SPIE (February 28 2005)

Back to Top