Paper
13 May 2019 Rapid prototyping of single-photon-sensitive backside-illuminated silicon avalanche photodiode arrays
Kevin K. Ryu, K. Alexander McIntosh, Steven Rabe, Joseph Ciampi, Renee D. Lambert, Rabindra Das, Bradley Felton, David Volfson, Christopher W. Leitz, Daniel R. Schuette, Brian F. Aull
Author Affiliations +
Abstract
We have developed a new approach for rapid die-level hybridization of backside-illuminated silicon avalanche photodiode (APD) arrays to CMOS readout integrated circuits (ROICs). APD arrays are fabricated on a custom silicon-on-insulator (SOI) wafer engineered with a built-in backside contact and passivation layer. The engineered APD substrate structure facilitates uniform APD substrate removal by selective etching at the die level after bump bonding. The new integration process has the following advantages over wafer-level 3D integration: 1) reduced cost per development cycle since a dedicated full-wafer ROIC fabrication is not needed, 2) compatibility with existing ROICs that are in chip-format from previous fabrication runs, and 3) accelerated schedule. The new approach is applied to produce 32×32 100-μm-pitch silicon GmAPD arrays. Electrical performance of the APD arrays show 100% pixel connectivity and excellent yield before and after substrate removal.
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Kevin K. Ryu, K. Alexander McIntosh, Steven Rabe, Joseph Ciampi, Renee D. Lambert, Rabindra Das, Bradley Felton, David Volfson, Christopher W. Leitz, Daniel R. Schuette, and Brian F. Aull "Rapid prototyping of single-photon-sensitive backside-illuminated silicon avalanche photodiode arrays ", Proc. SPIE 10980, Image Sensing Technologies: Materials, Devices, Systems, and Applications VI, 109800L (13 May 2019); https://doi.org/10.1117/12.2520798
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KEYWORDS
Avalanche photodetectors

Semiconducting wafers

Silicon

Readout integrated circuits

Etching

Oxides

Avalanche photodiodes

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