Novel CCD Image Processor For Z-Plane Architecture

S. E. Kemeny; E.S. Eid; E. R. Fossum

doi:10.1117/12.960372

13 September 1989 Novel CCD Image Processor For Z-Plane Architecture

S. E. Kemeny, E.S. Eid, E. R. Fossum

Proceedings Volume 1097, Materials, Devices, Techniques, and Applications for Z-Plane Focal Plane Array; (1989) https://doi.org/10.1117/12.960372
Event: SPIE 1989 Technical Symposium on Aerospace Sensing, 1989, Orlando, FL, United States

Abstract

The use of charge-coupled device (CCD) circuits in Z-plane architectures for focal-plane image processing is discussed. The low-power, compact layout nature of CCDs makes them attractive for Z-plane application. Three application areas are addressed; non-uniformity compensation using CCD MDAC circuits, neighborhood image processing functions implemented with CCD circuits, and the use of CCDs for buffering multiple image frames. Such buffering enables spatial-temporal image transformation for lossless compression.

Citation Download Citation

S. E. Kemeny, E.S. Eid, and E. R. Fossum "Novel CCD Image Processor For Z-Plane Architecture", Proc. SPIE 1097, Materials, Devices, Techniques, and Applications for Z-Plane Focal Plane Array, (13 September 1989); https://doi.org/10.1117/12.960372

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