Paper
21 March 2017 Rules-based correction strategies setup on sub-micrometer line and space patterns for 200mm wafer scale SmartNIL process within an integration process flow
H. Teyssedre, S. Landis, P. Brianceau, M. Mayr, C. Thanner, M. Laure, W. Zorbach, M. Eibelhuber, L. Pain, M. Chouiki, M. Wimplinger
Author Affiliations +
Abstract
In this paper the rules-based correction strategies for the nanoimprint lithography (NIL) technology are addressed using complete Scanning Electron Microscopy (SEM) characterizations. Performed onto 200 mm wafers imprinted with the HERCULES NIL equipment platform, Critical Dimension (CD) uniformity analyses are used to measure the evolution of lines and spaces features dimensions from the master to 50 consecutive imprints. The work brings focus on sub micrometer resolution features with duty cycles from 3 to 7. The silicon masters were manufactured with 193 optical lithography and dry etching and were fully characterized prior to the imprint process. Repeatability tests were performed over 50 wafers for two different processes to collect statistical and comparative data. The data revealed that the CD evolutions can be modelled by quadratic functions with respect to the number of imprints and feature dimension (CD and pitch) on the master. These models are used to establish the rules-based corrections for lines arrays in the scope of nanoimprint master manufacturing, and it opens the discussion on the process monitoring through metrology for the nanoimprint soft stamp technologies.
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H. Teyssedre, S. Landis, P. Brianceau, M. Mayr, C. Thanner, M. Laure, W. Zorbach, M. Eibelhuber, L. Pain, M. Chouiki, and M. Wimplinger "Rules-based correction strategies setup on sub-micrometer line and space patterns for 200mm wafer scale SmartNIL process within an integration process flow", Proc. SPIE 10144, Emerging Patterning Technologies, 101440V (21 March 2017); https://doi.org/10.1117/12.2260002
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Cited by 1 scholarly publication.
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KEYWORDS
Nanoimprint lithography

Critical dimension metrology

Semiconducting wafers

Manufacturing

Etching

Silicon

Metrology

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