Image Processing System With Time Shared Multiframe Data Bus Architecture: MFIP

S. Sugimoto; K. Matsuoka; Y. Ichioka

doi:10.1117/12.937007

9 January 1984 Image Processing System With Time Shared Multiframe Data Bus Architecture: MFIP

S. Sugimoto, K. Matsuoka, Y. Ichioka

Proceedings Volume 0435, Architectures and Algorithms for Digital Image Processing; (1984) https://doi.org/10.1117/12.937007
Event: 27th Annual Technical Symposium, 1983, San Diego, United States

Abstract

A general purpose, high-speed image processing system with a time shared multiframe data bus architecture and with multi-processors--MFIP--has been developed. Massive image data can be transferred from/to multiple memory modules to/from multi-processors through the high-speed time shared multiframe data bus (40 MW/sec). The system is built up, centering on 2MW large image memory consisting of eight memory modules with 256KW (1W = 16 bits). Image memory can be expanded up to 8MW, i.e., 32 memory modules. This paper describes the gross architecture of MFIP, and functional and operational features of the high-speed time shared multiframe data bus. Then design concept and manufacture of two image processing units, A and B in the system are presented.

Citation Download Citation

S. Sugimoto, K. Matsuoka, and Y. Ichioka "Image Processing System With Time Shared Multiframe Data Bus Architecture: MFIP", Proc. SPIE 0435, Architectures and Algorithms for Digital Image Processing, (9 January 1984); https://doi.org/10.1117/12.937007

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