To achieve timely and accurate fault detection, neural network-based time series modeling is applied to a reactive ion etching (RIE) process using an in-situ plasma sensor called optical emission spectroscopy (OES). OES is a wellestablished method of etch endpoint detection, but the large volume of data generated by this technique makes further analysis challenging. To alleviate this concern, principal component analysis (PCA) is adopted for dimensionality reduction of a voluminous OES data set, and the reduced data set is utilized for time series modeling and malfunction identification using neural networks. Four different RIE subsystems (RF power, chamber pressure, and two gas flow systems) were considered, and multiple degrees of potential faults were tested. The time series neural networks (TSNNs) are trained to forecast future process conditions, and those forecasts are compared to established baselines. Satisfying results are achieved, demonstrating the potential of this technique for real-time fault detection and diagnosis.

This numerical study focused on the errors that can occur when ellipsometric spectroscopic scatterometry programs are used for critical dimension (CD) control and other significant geometrical parameters. The role of the number of wavelengths, the measurements noise and the spectral range is analyzed in terms of CD precision. Conversely, an important part is devoted to the effect of a bad shaping modelling of the lines (corner rounding, foot and notch effects) and bad characterization of the index. We show that the scatterometry technique is very resistant to measurement noise, even for a small number of wavelengths, although the spectral range has an important role on the CD calculation. We also give quantitative data about the accuracy needed on refractive index of the diffracting material must. Excepted for profiles with additional feet, the CD found is very close to the original line without geometrical defects (corner rounding and notches).

This paper presents the concept of "copy result exactly" frameworks using EB-SCOPE technology which must be a powerful tool for coping the best process condition producing ever lasting good contact and via hole.

Assumption of the underlying probability distribution is an essential part of effective process control. In this article, we demonstrate how to improve the effectiveness of equipment monitoring and process induced defect control through properly selecting, validating and using the hypothetical distribution models. The testing method is based on probability plotting, which is made possible through order statistics. Since each ordered sample data point has a cumulative probability associated with it, which is calculated as a function of sample size, the assumption validity is readily judged by the linearity of the ordered sample data versus the deviate predicted by the assumed statistical model from the cumulative probability. A comparison is made between normal and lognormal distributions to illustrate how dramatically the distribution model could affect the control limit setting. Examples presented include defect data collected on SP1 the dark field inspection tool on a variety of deposited and polished metallic and dielectric films. We find that the defect count distribution is in most cases approximately lognormal. We show that normal distribution is an inadequate assumption, as clearly indicated by the non-linearity of the probability plots. Misuse of normal distribution leads to a too optimistic process control limit, typically 50% tighter than suggested by the lognormal distribution. The inappropriate control limit setting consequently results in an excursion rate at a level too high to be manageable. Lognormal distribution is a valid assumption because it is positively skewed, which adequately takes into account the fact that defect count distribution is typically characteristic of a long tail. In essence, use of lognormal distribution is a suggestion that the long tail be treated as part of the process entitlement (capability) instead of process excursion. The adjustment of the expected process entitlement is reflected and quantified by the skewness of lognormal distribution, yielding a more realistic estimate (defect count control limit). It is of particular importance to use a validated probability distribution when the sample size is small. Statistical process control (SPC) chart is generally constructed on the assumption of normality of the underlying population. Although this assumption is not true, as we discussed in the previous paragraph, the sample average will follow a normal distribution regardless of the underlying distribution according to the central limit theorem. However, this practice requires a large sample, which is sometimes impractical, especially in the stage of process development and yield ramp-up, when the process control limit is and has to be a moving target, enabling a rapid and constant yield-learning with minimal amount of production interruption and/or resource reallocation. In this work, we demonstrate that a validated statistical model such as lognormal distribution allows us to monitor the progress in a quantifiable and measurable way, and to tighten the control limits smoothly and systematically. To do so, we use the verified model to make a deduction about the expected defect count at a predetermined deviate, say 3s. The estimate error or the range is a function of sample variation, sample size, and the confidence level at which the estimation is being made. If we choose a fixed sample size and confidence level, the defectivity performance is explicitly defined and gauged by the estimate and the estimate error.

An automated surface inspection system, KLA-Tencor SP1-TBI, was used to investigate the surface defectivity of three different sets of bare silicon wafers, in order to test the capability of the tool to distinguish between particles (removable defects) and pits, generally called COPs (Crystal Originated Particles). Two different type of MEMC products have been investigated: The Advanta wafers characterized by a low density of COPs and with an annular region at the edge of the wafer that is “free” of any agglomerated defect; A standard P100 polished material in which the COP defects are present on a large portion of the wafer surface almost with the same density. When the SP1-TBI discrimination algorithm is applied, real time defect classification (RTDC) is performed and the resulting wafer map displays simultaneously but differently particles and COPs due to their different scattering behavior. The validation of the SP1-TBI scan results has been performed in two ways. The first one making a pre to post cleaning comparison and the second one by Optical and Atomic Force Microscope investigation. In both cases the confidence level of the algorithm is depending on the material investigated but is generally greater then 90% allowing considering the SP1-TBI algorithm as a good system to distinguish particles from COPs.

An electron beam inspection is strongly required for HARI to detect contact and via defects that an optical inspection cannot detect. Conventionally, an e-beam inspection system is used as an analytical tool for checking the process margin. Due to its low throughput speed, it has not been used for in-line QC. Therefore, we optimized the inspection area and developed a new auto defect classification (ADC) to use with e-beam inspection as an in-line inspection tool. A 10% interval scan sampling proved able to estimate defect densities. Inspection could be completed within 1 hour. We specifically adapted the developed ADC for use with e-beam inspection because the voltage contrast images were not sufficiently clear so that classifications could not be made with conventional ADC based on defect geometry. The new ADC used the off-pattern area of the defect to discriminate particles from other voltage contrast defects with an accuracy of greater than 90%. Using sampling optimization and the new ADC, we achieved inspection and auto defect review with throughput of less than 1 and one-half hours. We implemented the system as a procedure for product defect QC and proved its effectiveness for in-line e-beam inspection.

The formation of scratches during the chemical mechanical polishing (CMP) of Copper (Cu) interconnects is inevitable. As interconnect dimensions shrink with each successive technology node, the impact of these CMP induced scratches is expected to become more severe. A three-step Cu CMP process was investigated in terms of scratch formation on the various polishing platens. Two characteristic types of microscratches can be found after the Cu CMP process. They are long microscratches and triangle microscratches. The study shows that the microscratches generated by platen 1 tend to be deeper than those generated by platen 2, and they can remain even after passing through platens two and three. The effects of polishing pressure and polishing speed on microscratch formations are unclear. Therefore, the most likely reason for platen 1 generating deeper microscratches is due to the use of larger and harder abrasive particles. In addition, it was also noticed that the occurrence of microscratches could increase due to the agglomeration of alumina abrasive particles into larger particles. Flushing off the stagnant slurry in the slurry line to remove the agglomerated abrasive particles prior to actual polishing is effective in reducing the incidence of scratching.

This paper describes the validation of the methodology, the model and the impact of an optimized Lithography Defect Monitoring Strategy at two different semiconductor manufacturing factories. The lithography defect inspection optimization was implemented for the Gate Module at both factories running 0.13-0.15μm technologies on 200mm wafers, one running microprocessor and the other memory devices. As minimum dimensions and process windows decrease in the lithography area, new technologies and technological advances with resists and resist systems are being implemented to meet the demands. Along with these new technological advances in the lithography area comes potentially unforeseen defect issues. The latest lithography processes involve new resists in extremely thin, uniform films, exposing the films under conditions of highly optimized focus and illumination, and finally removing the resist completely and cleanly. The lithography cell is defined as the cluster of process equipment that accomplishes the coating process (surface prep, resist spin, edge-bead removal and soft bake), the alignment and exposure, and the developing process (post-exposure bake, develop, rinse) of the resist. Often the resist spinning process involves multiple materials such as BARC (bottom ARC) and / or TARC (top ARC) materials in addition to the resist itself. The introduction of these new materials with the multiple materials interfaces and the tightness of the process windows leads to an increased variety of defect mechanisms in the lithography area. Defect management in the lithography area has become critical to successful product introduction and yield ramp. The semiconductor process itself contributes the largest number and variety of defects, and a significant portion of the total defects originate within the lithography cell. From a defect management perspective, the lithography cell has some unique characteristics. First, defects in the lithography process module have the widest range of sizes, from full-wafer to suboptical, and with the largest variety of characteristics. Some of these defects fall into the categories of coating problems, focus and exposure defects, developer defects, edge-bead removal problems, contamination and scratches usually defined as lithography macro defects as shown in Figure 1. Others fall into the category of lithography micro defects, Figure 2. They are characterized as having low topography such as stains, developer spots, satellites, are very small such as micro-bridging, partial micro-bridging, micro-bubbles, CD variation and single isolated missing or deformed contacts or vias. Lithography is the only area of the fab besides CMP in which defect excursions can be corrected by reworking the wafers. The opportunity to fix defect problems without scrapping wafers is best served by a defect inspection strategy that captures the full range of all relevant defect types with a proper balance between the costs of monitoring and inspection and the potential cost of yield loss. In the previous paper [1] it was shown that a combination of macro inspection and high numerical aperture (NA) brightfield imaging inspection technology is best suited for the application in the case of the idealized fab modeled. In this paper we will report on the successful efforts in implementing and validating the lithography defect monitoring strategy at two existing 200 mm factories running 0.15 μm and 0.13 μm design rules.

No abstract available.

Contamination around the edge exclusion area and bevel of silicon wafers is becoming an increasingly important area to control in semiconductor manufacturing. This is especially relevant in any manufacturing line where portions of the process toolset, e.g. metrology or lithography, are shared between multiple types of materials processed. This could be materials like copper versus aluminum for interconnect lines or more recently the newer high-k gate dielectrics and alternate metal electrodes. There are numerous pathways for contamination; for example, one source could be incomplete etching of a film at the edge during a backside-cleaning process. Also, the move to edge handling of wafers along with wafer alignment and centering pins is a contamination pathway. Even the direct contact between the wafer's edge and the cassette it is in can be a source of cross contamination. Historically, it has been difficult or impossible to quantify metal contamination in the bevel and edge exclusion region of silicon wafers by traditional analytical methods. Total reflection x-ray fluorescence spectroscopy cannot operate close to the edge of a wafer due to scattering affects of the incident radiation and typically has a built in edge exclusion area of 10 mm. Vapor phase decomposition would expose the entire wafer to hydrofluoric acid vapor, which would not be desired on a patterned wafer or a wafer with a film that would reacted with the vapor. Direct acid drop decomposition and vapor phase decomposition both employ a scanning technique where it is impossible to include the bevel area for analysis. Time of flight secondary ion mass spectrometry is also not easily done on the angled bevel edge of a wafer. The relative sample size of a time of flight mass spectrometer analysis is also quite small and therefore would require many analyses to achieve a sampling set that is representative of the entire edge of a wafer. We have developed a technique that will allow us to precisely measure the metallic contamination in this difficult region on both 200 mm and 300 mm wafers. This procedure calls for exactly positioning the wafer in a mechanical jig and collecting the contamination via chemical extraction. The amount of the wafer's edge exclusion analyzed is controllable as well as the ability to analyze the entire circumference of the wafer or any portion thereof. The solution sample is then analyzed for trace metals by inductively coupled plasma mass spectrometry. Knowing the concentration of the metals in solution, the mass of the solution, and the area of the wafer analyzed we will calculate the area concentration in atoms/cm^2 for comparison to the traditional techniques mentioned in the previous paragraph. We will show the development of this technique along with data highlighting contamination control in a manufacturing line that processes multiple types of material. Detection limits of this technique and current challenges under development will be discussed. This technique is likely to become an indispensable part of any semiconductor fabÕs analytical capabilities.

In semiconductor device manufacturing, critical dimension (CD) metrology provides a measurement for precise line-width control during the lithographic process. Currently scanning electron microscope (SEM) tools are typically used for this measurement, because the resolution requirements for the CD measurements are outside the range of optical microscopes. While CD has been a good feedback control for the lithographic process, line-widths continue to shrink and a more precise measurement of the printed lines is needed. With decreasing line widths, the entire sidewall structure must be monitored for precise process control. Sidewall structure is typically acquired by performing a destructive cross sectioning of the device, which is then imaged with a SEM tool. Since cross sectioning is destructive and slow, this is an undesirable method for testing product wafers and only a small sampling of the wafers can be tested. We have developed a technique in which historical cross section/top down image pairs are used to predict sidewall shape from top down SEM images. Features extracted from a new top down SEM image are used to locate similar top downs within the historical database and the corresponding cross sections in the database are combined to create a sidewall estimate for the new top down. Testing with field test data has shown the feasibility of this approach and that it will allow CD SEM tools to provide cross section estimates with no change in hardware or complex modeling.

The measurement of line-edge roughness (LER) has recently become a major topic of concern in the litho-metrology community and the semiconductor industry as a whole, as addressed in the 2001 International Technology Roadmap for Semiconductors (ITRS) roadmap. The Advanced Metrology Advisory Group (AMAG, a council composed of the chief metrologists from the International SEMATECH (ISMT) consortium’s Member Companies and from the National Institute of Standards and Technology (NIST) has begun a project to investigate this issue and to direct the critical dimension scanning electron microscope (CD-SEM) supplier community towards a semiconductor industry-backed solution for implementation. The AMAG group has designed and built a 193 nm reticle that includes structures implementing a number of schemes to intentionally cause line edge roughness of various spatial frequencies and amplitudes. The lithography of these structures is in itself of interest to the litho-metrology community and will be discussed here. These structures, along with several other photolithography process variables, have been used to fabricate a set of features of varying roughness value and structure which span the LER process space of interest. These references are, in turn, useful for evaluation of LER measurement capability. Measurements on different CD-SEMs of major suppliers were used to demonstrate the current state of LER measurement. These measurements were compared to roughness determined off-line by analysis of top-down images from these tools. While no official standard measurement algorithm or definition of LER measurement exists, definitions used in this work are presented and compared in use. Repeatability of the measurements and factors affecting their accuracy were explored, as well as how CD-SEM parameters can affect the measurements.

It is shown that the focused ion beam in the Physical Electronics SMART-Tool can be used to create the conditions needed to locate interconnect defects by voltage-contrast analysis. The SMART-Tool is designed for the analysis of small defects on full wafers by Auger electron spectroscopy. These defects are typically located using a defect coordinate map from a light-scattering based inspection tool. The SMART-Tool can be equipped with a focused ion beam for cross-sectioning defects. Stand-alone focused ion beam tools have been used to locate defects by voltagecontrast analysis. Unlike stand-alone tools, the ion beam in the SMART-Tool is situated off the surface normal. This does not hinder its ability to ground interconnect parts to the substrate, creating the conditions for passive voltagecontrast imaging. A defective via chain, identified by high resistivity on parametric test, was grounded to the substrate by focused ion beam milling in the SMART-Tool. The defective via was then identified by voltage contrast in images. The defect was marked and cross-sectioned by the focused ion beam and analyzed by Auger electron spectroscopy, all in the SMART-Tool without breaking or repositioning the wafer. Studies suggest that unbroken wafers can be returned to the manufacturing line to complete processing after focused ion beam milling without compromising unaffected die. Thus, this type of interconnect defect analysis can be performed on defective die without sacrificing non-defective die on the same wafer.

X-Ray Reflectometry (XRR) is a glancing angle technique to characterize thickness, density, and surface/interface roughness of thin stacks of transparent and opaque materials. XRR does not require prior knowledge of n and k, from which thickness values are derived using optical techniques. This study examines the effects of process parameters (including gas flows, RF power, deposition time, and pressure) on bulk and surface film properties using XRR. The films comprised of single- / multi-station deposition of SiON films with post-deposition surface treatment in an N₂O plasma for anti-reflective coating (ARC) applications in UV/photolithography. The understanding of ARC films and the treatments used to reduce the nitrogen content in the skin film portion of the ARC is critical for minimizing the amount of residual photoresist or "footing" seen after develop. Multi-site measurements were done on a commercial x-ray reflectometer designed for high-volume production processes. The results from these measurements describe the sensitivity of the XRR technique to interfacial/skin layers and explore this method as an alternative to conventional optical techniques. The ability to identify minute differences within the same film (for example, in a multi-station deposition process) using XRR offers advanced process control/failure analysis possibilities.

As the semiconductor industry continues the transition to 300mm wafer factories, not only does the cost per wafer increase dramatically, but the number of eligible die (assuming equal die size) more than doubles. Given the parallel transition to design rules of 90nm and below, both the cost of production and the potential revenue from a 300mm wafer are vastly higher than that of a current 200mm wafer. For this reason alone, it is essential that wafer jeopardy, or the number of wafers processed between metrology events, be reduced dramatically from the levels in a typical 200mm wafer line. The most promising method for achieving this is process tool-integrated metrology. Such systems allow rapid (in some cases near instantaneous) feedback on the process. Such a data stream, as input to an Advanced Process Control (APC) system, provides a volume of data and feedback lag time unparalleled by standalone metrology. In this case, critical dimension (CD) metrology is provided by a scatterometer integrated on a 200mm TEL CLEAN TRACK - ACT 8. The data, available on a wafer-by-wafer basis, is uploaded to the factory host where the APC application can update its state estimation before the entire lot has even completed processing.

We will present a complete example that demonstrates daily CD monitor for good CDSEM control, including sampling plan, monitoring procedure, and monitoring and matching data for multiple CDSEM. In addition, we also investigate two methods to address the carbon contamination problem. In the first method, carryover trends on three different film stacks, poly, metal, and multi-layer metal, before and after plasma clean are compared in search of ways to minimize carryover. The second method applies statistical treatment to remove the effect of carryover while maintaining sensitivity over small fluctuations in line CD monitor results. Both linear regression and exponentially weighed moving average calculated from daily monitor data are used to model the baseline carryover trend for the purpose of isolating tru tool variability. Using this method, we can easily quantify the long-term stability of each CDSEM, and with that, we are able to calculate the true long-term process variation Cp by subtracting the CDSEM variation component from the observed total Cp.

Non-visual defects are anomalies that result in electrical fail at final wafer test but are not detectable in-line with the current optical defect detection tool set. These defects have been found to constitute a major potion of the list of reasons for electrical yield loss. Non-visual defects may be so small they are beyond the resolution of available optical tools, they may have no physical remnant, they may be mechanical or electrical in nature, or they may be due to subtle process variations, or parametric variations. In order to understand the exact nature of the non-visual defect problem, International SEMATECH (ISMT) conducted an industry survey of eight major semiconductor device manufacturers. The 2002 "Non-visual Defect Detection Survey" was designed to determine which specific levels, processes, and defect types are of most concern to semiconductor manufacturers for causing non-visual defects. In this paper, the major observations, issues, and recommendations that resulted from the survey will be presented, as well as directions for future non-visual defect detection based on survey results.

Defect inspection metrology is an integral part of the yield ramp and process monitoring phases of semiconductor manufacturing. High aspect ratio structures have been identified in the ITRS as critical structures where there are no known manufacturable solutions for defect detection. We present case studies of a new inspection technology based on digital holography that addresses this need. Digital holography records the amplitude and phase of the wavefront from the target object directly to a single image acquired by a CCD camera. Using deep ultraviolet laser illumination, digital holography is capable of resolving phase differences corresponding to height differences as small as several nanometers. Thus, the technology is well suited to the task of finding defects on semiconductor wafers. We present a study of several defect detection benchmark wafers, and compare the results of digital holographic inspection to other wafer inspection technologies. Specifically, digital holography allows improved defect detection on high aspect ratio features, such as improperly etched contacts. In addition, the phase information provided by digital holography allows us to visualize the topology of defects, and even generate three-dimensional images of the wafer surface comparable to scanning electron microscope (SEM) images. These results demonstrate the unique defect detection capabilities of digital holography.

The ability to detect killer defects on the Semiconductor Manufacturing Industry "in line" will require resolution below 30nm by 2005. It has been assumed that optical inspection, which has been the standard tool for such applications for almost two decades and which has enabled inspection throughputs of the order of 60 wafers per hour, cannot meet this challenge. In this paper we show that the limits of optical inspection have not been reached and that therefore existing, cost-effective, mature laser technology can still be exploited to perform fast optical inspection down to the 15nm range. This breakthrough involves the wave interrogated near-field array, a new paradigm in optical inspection that combines the resolution of near-field detection with the efficiency of far-field detection. Full-physics numerical simulations are used to show that: (1) Resonant photonic antennas can amplify the scattered signal from sub-wavelength defects by over three orders of magnitude. (2) Such antennas can also discern the composition of the defect. (3) Holographic filtering of the array's scattered signal easily locates a single defect within the scanning area of the entire array. A scaled-up experiment at microwave frequencies has been performed to prove the feasibility of this technique.

Faster time to results is becoming more and more critical for chip makers to build up the production monitoring capability on advanced process development. Especially for SiGe's process, which uses SEG process by adding germanium. SiGe products provide higher frequency and lower power dissipation than traditional Si based products due to lower energy band-gap. SiGe process can be integrated to current semiconductor process easily with lower cost comparing to GaAs process. The combination of HBT and CMOS is excellent on wireless and optical fiber communication application. This application introduce a SiGe's in-line measurement method by using spectroscopy ellipsometer, which offers a non-destructive and ultra fast measurements than typical metrology tools, such like RBS, XRD or SIMS, on both box profile and gradient profile of varied Ge concentration of the films. By characterizing the different RI interval of the dispersion curves of SiGe-films, single or multi layers, through spectroscopy ellipsometer, we may estimate the film thickness and the peak concentration of germanium. A correlation of this in-line method with off-line method, such as XRD or SIMS, is provided through different RI-intervals of SiGe films as a comparison. The content of this paper offered experimental measurements data, which is not only on monitor wafers but also on production wafers including different box and gradient profiles of Ge concentration of the SiGe films via spectroscopy ellipsometer.The optical method is highly reducing the fabrication costs and accelerating production yields.

We have developed a proof of concept system, utilizing a projection electron microscope for the next generation EB inspection system. In this POC system, the image quality of secondary electrons is quite sensitive to the homogeneity of wafer surface potential. In logic devices with a random pattern layout, both image distortion and inhomogeneous image contrast are serious problems. By homogenizing the wafer surface potential with negative charging of the semiconductor device, we could eliminate image distortion and inhomogeneous image contrast using a pretreatment dosage of 12 mC/cm2. Furthermore, by imaging the reflection electrons with 4000 V, a high image quality can be obtained, even with contact/via layers. By selecting the optimum energy of the imaging electrons, the imaging capability of this EB inspection system could be widely improved. We can also confirm the practicality of this technology for wafer inspection of ULSI devices.

Ion beam implantation of silicon with hydrogen is a method of producing thin silicon films for the manufacture of silicon on insulator (SOI) wafers. The implanted hydrogen depth profiles are traditionally measured using nuclear reaction analysis (NRA) or secondary ion mass spectrometry (SIMS) which have the disadvantages of requiring specialized equipment and, in the case of SIMS, being a destructive measurement. In the current work, a simplified method of measuring the depth profile of implanted hydrogen ions in silicon has been developed. Using a spectroscopic ellipsometer, optical data are collected from hydrogen implanted silicon wafers in a non-contact and non-destructive manner. The ellipsometric data from 600-980 nm wavelength are then analyzed by modeling the damage as a graded sub-surface layer in the silicon. By fitting this model to the experimental data, values for the depth of the implantation and the width of the implantation distribution can be extracted. This method offers the advantages of being repeatable, fast, and non-destructive, as well as using a piece of metrology equipment readily available in most semiconductor fabs. The method has been tested over a range of implant energies (24-92 keV) and hydrogen doses and shows excellent correlation to traditional NRA measurements for implant depth profile.

In the competitive world of semiconductor manufacturing today, control of the process and manufacturing equipment is paramount to success of the business. Consistent with the need for rapid development of process technology, is a need for development wiht respect to equipment control including defect metrology tools. Historical control methods for defect metrology tools included a raw count of defects detected on a characterized production or test wafer with little or not regard to the attributes of the detected defects. Over time, these characterized wafers degrade with multiple passes on the tools and handling requiring the tool owner to create and characterize new samples periodically. With the complex engineering software analysis systems used today, there is a strong reliance on the accuracy of defect size, location, and classification in order to provide the best value when correlating the in line to sort type of data. Intentional Defect Array (IDA) wafers were designed and manufacturered at International Sematech (ISMT) in Austin, Texas and is a product of collaboration between ISMT member companies and suppliers of advanced defect inspection equipment. These wafers provide the use with known defect types and sizes in predetermined locations across the entire wafer. The wafers are designed to incorporate several desired flows and use critical dimensions consistent with current and future technology nodes. This paper briefly describes the design of the IDA wafer and details many practical applications in the control of advanced defect inspection equipment.