We present an overview of in-line monitoring of chemical- mechanical polishing (CMP) processes. We discuss the technical challenges and review many of the approaches that have been published. Several methods are currently under investigation including optical, thermal (pad temperature), friction (torque motor current), electrochemical, and acoustic (vibration).

Shallow trench isolation (STI) process has become an architectural requirement for sub 0.25 micron device rules, as localized oxidation of silicon (LOCOS) does not deliver the benefits from smaller design rule. The challenge of STI is not only typically to planarize a high-density plasma oxide and SiN using CMP (Chemical Mechanical polish) process in the same time, but also to reduce STI process associated defects, which could cause yield loss and reliability issues. In a typical CMOS fabrication flow, STI module is usually the very first process module in the whole process. Therefore, detect, characterize, and reduce the STI CMP related defect is very important. Because it is not only to improve yield and reliability, but also to reduce the background noise in defect monitoring for the rest of the front-end processes lines. A methodology for in-line STI defect identification, reduction using KLA array mode and AIT with RMBT, has been developed for yield enhancement at VLSI/Philips. This paper also details the implementation of in-line defect inspection in STI process module. STI CMP process parameters related to the defects have been investigated to improve yield and reliability.

This paper presents an iterative algorithm that merges the physical layout of a circuit with an optical test structure called a wire segment hologram. Wire segment holograms are geometrical patterns that resemble circuit wiring but are arranged to project an holographic image when illuminated with a light source whose wavelength is comparable to the feature size of the process under test. The quality of the projected image is strongly correlated with the fidelity of the fabrication process and therefore provides rapid, non-contact, dimensional metrology. We propose that the merged circuit/test structure is ideal for metal processing which suffers from high pattern dependence, such as chemical mechanical polishing. By changing the relative width, height and pitch of the merged diffractive elements, it is possible to generate test structures with a wide range of metal density. Thus, these test structures can perform the dual task of reducing pattern dependent defect formation and characterizing the dimensional fidelity of the fabrication process. Initial results are presented that indicate the merged circuit/test structures can resolve mask offset variations as small as 0.1 micrometer for a 2 micrometer wire width.

Defect reduction and yield enhancements are increasingly critical for advanced DUV lithography used in semiconductor manufacturing. The key to achieving defect reduction and maximizing yield is to focus on the developer module of the Track where the majority of defects are created. For optimum defect reduction, the rinse nozzle should provide good liquid distribution, uniform coverage of wafer, excellent rinsing action and low impact on wafer. The developer catch cup chamber should provide an uniform air velocity field to reduce turbulence, backflow and recirculation. An optimized process to leverage maximum benefit from rinse nozzle and catch cup chamber is also required. A solution to meet these requirements is presented here. This approach resulted in reducing defect counts by a factor of two along with a simultaneous reduction in develop process time by 23% and wider process latitude. In the advanced DUV 248 nm era, for 130 - 180 nm geometries using extremely sensitive and high contrast resists, understanding and minimizing the contribution of the developer process to CD control is very critical. The key components to improve CD control are enhanced developer nozzle in conjunction with develop process optimization. The developer nozzle should provide uniform coverage and result in low impact on wafer. This enables significant CD uniformity improvement without compromising defect reduction and yield enhancement. An all low impact chemical delivery (rinse and develop) system was designed to eliminate pattern collapse of 180 - 130 nm features. A solution to meet these requirements is presented here. The develop rate uniformity was improved by 30% for both Acetal- based type A resist and ESCAP-based type B resist. CD uniformity was improved by 25% for type A resist. The uniqueness of this project is an integrated and synergistic approach to yield and CD control for advanced DUV lithography, to maximize semiconductor-manufacturing productivity.

The semiconductor industry has been full of news regarding the transition to 300 mm wafers. In 1998, SEMICONDUCTOR300 (SC300) was the first to demonstrate the capability to produce integrated products on 300 mm wafers. To meet the challenge of maintaining quality while simultaneously reducing cost and ramping SC300 into pilot manufacturing, the authors have investigated the use of an overlay implant technique. A single 300 mm wafer is used to collect particle, high dose, and low dose information from a Eaton GSD HE-3 ion implanter. The implants, a high dose As+ 80 KeV 3E14 followed by a low dose As+ 60 KeV 3E11 damage implant, are measured using a KLA/Tencor Rs100 sheet resistance measurement tool with a 3 mm edge exclusion. In addition to verifying the technique at 300 mm, the paper presents overlay implant data collected using externally reclaimed wafers, currently one third the cost of prime 300 mm wafers, and explores the possibility of reusing implanted monitor wafers by re-annealing the wafers and repeating the low dose damage implant. Initial data is also presented for implants performed on the backside of 300 mm wafers.

Vacuum-level problems in semiconductor process tools -- from leaks or contamination -- can significantly reduce product yield and tool availability if not detected quickly. Here we present a portable and compact plasma sensor which can monitor the fingerprint of effluent from the process chamber to the exhaust piping by optical emission spectroscopy. The device and tests to monitor and control semiconductor process are described. Further applications such as effluent treatment are tackled.

Plasma etch has always played an important role in microelectronic manufacturing. Defects observed at post-etch usually have significant impact on yield. The visual post-etch defects are generally divided into three major categories. Those defects discovered at etch but not generated by etch, the defects generated during etch, and the defects generated by interaction between different process layers. The prior layer defects are the defects uncovered by the etch process but originated in prior layers such as film or lithography. The true plasma etch-generated defects usually consist of process-induced defects and equipment defects. Process integration defects are those type of defects that are caused by interaction between different layer stoichiometry and process chemistry. The origin of these defects observed at post-etch need to be identified and isolated in order to make defect reduction in the plasma etch area manageable. The best defect yield management strategy is to use an integrated monitoring scheme consisting of in-line, short-loop, and equipment monitor wafers to monitor defect levels in the production line and to troubleshoot yield loss caused by defects. This paper discusses how to set up effective integrated short-loop patterned etch and blank resist-coated etch equipment monitors to isolate the contribution of different components of post-etch defects listed above.

SEM-based defect characterization is a critical technology for wafer manufacturers and others using unpatterned wafers for process monitoring. One of the main drivers of this technology is the need to characterize increasingly smaller defects whose dimensions scale with the shrinking design rules of semiconductor devices. Light-scattering based inspection tools (e.g. KLA/Tencor 6200, SP1) are used to detect defects on the wafer surface and to output a file which contains the xy coordinates of defects relative to the wafer's alignment features. The wafer and defect file are then transferred to the SEM review tool. The defect file is transformed into the coordinate system of the SEM's xy stage in two steps: first an approximate transformation is performed based on the wafer's orientation on the SEM's stage, and then, after several defects have been located, a more accurate transformation is performed using two or more updated defect coordinates. Review of further defects then proceeds and may include high resolution imaging, cross sectioning, and chemical characterization by EDS. This above method can be tedious and somewhat unreliable. It depends largely on the accuracy of the defect file, which contains both systematic and random error. Searching is often required, and it is generally true that the smaller the defect, the more difficult it is to locate by SEM. In this paper, we will discuss the added value and drawbacks of employing a new sample preparation technique which uses precision surface marking and high accuracy defect mapping to minimize the difficulties of SEM-based defect review on unpatterned wafers.

The Surface Charge Profiler (SCP) has been introduced for monitoring and development of silicon epitaxial processes. The SCP measures the near-surface doping concentration and offers advantages that lead to yield enhancement in several ways. First, non-destructive measurement technology enables in-line process monitoring, eliminating the need to sacrifice production wafers for resistivity measurements. Additionally, the full-wafer mapping capability helps in development of improved epitaxial growth processes and early detection of reactor problems. As examples, we present the use of SCP to study the effects of susceptor degradation in barrel reactors and to study autodoping for development of improved dopant uniformity.

Semiconductor fabrication facilities rely on the integrity of the silicon to manufacture sub-micron devices. Cross contamination of P-type silicon to N-type carriers or vice versa in the near surface region of the silicon can be detrimental to device performance. Semiconductor processing typically includes numerous diffusion and pre-clean steps, any one of which might auto-dope P-type silicon substrate with phosphorous. Inline monitoring of these near surface doping effects enhances the ability to diagnose autodoping problems. A non-contact Corona Oxide Silicon (COS) measurement technique has the ability to detect cross-contaminated P-type silicon with phosphorous from wet clean benches and diffusion furnaces. Results show COS flatband (V_fb) and oxide total charge (Q_tot) measurements are sensitive to various levels of intentional phosphorous contamination implanted into the silicon at pre-oxidation. Phosphorous at the silicon/oxide interface can pile up and create an electrically active thin 'N' skin. Phosphorous from this thin 'N' skin is shown to change the electrical characteristics of near surface region of the silicon. The detection of unwanted phosphorus with the use of COS inline monitoring can greatly reduce the response time when auto-doping problems occur.

An extraction method of micro-contaminants detrimental for silicon (Si) devices and its impact on clean technology are elaborated to focus on upgrading device performances. Deleterious metal impurities on wafer surfaces such as Fe, Cu, Ni and Al are analyzed using an improved pack extraction method (PEM), in which sample wafers were enclosed in a cleaned teflon bag with aqueous acid solutions. Upon the extraction of impurities, three types of solutions [(I) HCl/H₂O, (II) HF/H₂O and (III) HF/HNO₃/H₂O], were successively replaced one after another in the cleaned teflon bag, resulting in measuring impurities on oxide surfaces, oxides and SiO₂-Si interfaces, separately. The monitoring of these harmful impurities helps feed back to reduce the impurities in device manufacturing processes.

Reduction of gate oxide thicknesses to the tunnelable range as well as the anticipated introduction of alternative gate dielectric materials create new challenges regarding monitoring of gate insulation processes. In this paper methodologies applied in gate oxide characterization are considered and advantages of non-contact methods are emphasized. More specifically, the Surface Charge Profiling (SCP) method, which is particularly well suited for this application is discussed. This method allows measurement of the charge density without any bias on the oxide, and hence, without any current flow across the oxide. Therefore, measurements of surface/oxide charge density as well surface recombination lifetime can be carried on oxides in which charge measurement using other methods would be prevented due to significant current. This capability of the SCP method is demonstrated using experimental results.

COCOS, corona oxide characterization of semiconductor, metrology provides for fast and economic non-contact characterization of oxide properties in IC fab lines. The technique employs the repeated application of corona charge in sequence with contact potential difference, CPD, measurements to obtain flatband, Tox, Cox, Dit, and other characteristics of the SiO₂ - Si system. Following a brief discussion of the underlying physical principles, specific examples of process induced defects and properties identified by the COCOS method will be presented. For example, process integrity monitoring is demonstrated with a process-tube sealing problem revealed by the correspondence between percent-thickness- uniformity and flatband data when oxide thickness varied by only a few angstroms. Characteristics of oxides annealed in a hydrogen containing ambient to remove damage are presented as examples of integration and process improvement efforts. Interface trap spectroscopy results using the new technique show that the anneal has a varied effect on traps depending on their position in the bandgap designated by the value of the surface barrier voltage. Such parametric data is rapidly obtained from re-usable monitor wafers run along with product, which results in increased equipment utilization. These and other encouraging results suggest that the COCOS methodology may enable the development of a better understanding of the key relationships between process conditions and the material properties produced by them.

Particles are transferred to wafer surfaces during application of spin-on dielectrics (SOD). Excessive particle levels on wafers are known to reduce device yield. Separate instruments using laser-light scattering techniques are used to assess liquid-born particles in SOD precursors and particles transferred to wafer surfaces in SOD processes. Experiment shows that, based on the particle concentration in the liquid, the number of liquid-borne particles dispensed onto the wafer is significantly larger than the number of particles measured on the wafer after SOD deposition. In experiments the obvious correlations expected between liquid-borne particle concentrations and wafer particle counts were not observed for the magnitude of liquid-borne particle concentrations commonly associated with modern VLSI device production. Two models are proposed to explain these observations. The models estimate the liquid-to-wafer particle transfer based on the liquid- borne particle concentration and the solids transferred either as a percent of total solids or as a percent of total volume. The models estimate that the number of particles transferred from even relatively high particle count spin-on dielectric liquid precursors challenge the measurement sensitivity/capability of the wafer surface scanning inspection station.

Transfer of semiconductor process steps from one Rapid Thermal Processing (RTP) system to another may cause severe problems due to non-matching pyrometers. Resulting temperature differences of alternatively used RTP machines despite identical process recipes can lead to process and yield problems. In this study we present two emissivity-independent methods for comparing and adjusting wafer temperatures of different RTP systems, one by monitoring titanium silicide (TiSi_x) sheet resistivities and the other by titanium film stress measurements. We perform sheet resistivity measurements on various titanium sputtered silicon wafers. TiSi_x formation is induced by RTP on an AST SHS 1000 and an AG HEATPULSE 4100 system in the temperature range between 680 degrees Celsius and 800 degrees Celsius, which is of particular interest for RTP nitridation of titanium as a diffusion barrier. Prior to resistivity measurement the unreacted titanium is selectively etched. We show how temperature differences of the two RTP systems can be deduced from different sheet resistivity values of AST and AG wafers processed at the same nominal temperatures as read on the respective pyrometer scales. Comparison of mechanical stress imposed on the wafers by titanium deposition and the subsequent RTP induced silicidation yield exactly the same temperature difference. Both methods offer fast, reliable and sensitive tools to observe and correct for potential temperature differences of different RTP systems and therefore comprise efficient means to avoid process and yield problems and enhance throughput.

A large variety of physical analysis techniques are used in the semiconductor industry to identify defects impacting yield or reliability. Identification of a defect often requires the combined use of several techniques to give a clear understanding of the defect nature. In the present study, several microscopy techniques (SEM, TEM, Analytical-TEM, AFM and FIB) have been intensively used to identify the origin of residues observed on the edge of large active areas in a low power CMOS technology. A KLA automatic inspection system has been used for locating and quantifying the defects. It has been shown that the defects are related to amorphous silicon residues whose origin is related to the gate deposition process. In the process, the polysilicon gate is deposited in two steps. A first thin amorphous silicon layer is deposited, through which the Vt implant is done, followed by the deposition of a thick polysilicon layer. Analysis of defaults showed that the residues are related to a non-uniform thin oxide layer located between the thick polysilicon layer and the underlying thin amorphous silicon, which halts the polysilicon gate etch. Thicker native oxide on amorphous silicon due to humidity or drying spots is the presumed source of the thin non-uniform oxide. Increasing the HF dip before the polysilicon deposition eliminated almost all residues. No negative effect on the oxide quality or other electrical parameter has been observed. Eliminating altogether the amorphous-Si gate deposition process is an even more robust solution.

Automated AFM (Atomic Force Microscope) has been used to characterize the structure of the HSG (hemi-spherical grain) polysilicon film. The structure characterization parameters such as the surface roughness, the grain size and density of the storage polysilicon were returned by AFM. In this paper we carried out designed experiments and characterized HSG samples with variant growth temperatures and doping densities. We compare the new AFM technique and the conventional optical reflectivity and SEM techniques. The results show that AFM data has a strong correlation with the electric response of the DRAM devices while the optical reflectivity and SEM measurements show weak or no correlation. Among the many data analysis performed by the AFM software, kurtosis and skewness were found to be valuable parameters for the optimization and control of both capacitance and ONO BV (breakdown voltage) of the DRAM devices.

It is critical for success in the microprocessor business to understand the relationship between yield and speed- performance. This paper outlines a method for modeling device speed distribution and yield using on-chip ring-oscillator measurements. The modeling method is used in production on the UltraSPARC^TM-II family of microprocessors. Lot-level speed distributions are predicted within 10% by speed-bin and quarterly distributions within 5% by speed-bin. Graphs are generated to show the relationship between business and process concerns.

A methodology is presented which dramatically enhances process development and yield improvement by using rapid in-line defect classification. This methodology is based on a wafer inspection tools, both optical and SEM, which provide classified defect counts not simply total defect count. A wafer inspection system (WF736) is used in combination with a high throughput defect-review SEM (SEMVision). This combination of tools provides rapid defect classification and source identification for process development and defect elimination. The WF736 generates defect classification during the inspection with no loss in throughput. The SEMVision allows for further detailed analysis and classification. In addition, patterned wafers are utilized for thorough defect capture and process studies. The methodology provides critical information for improved process development and analysis, as well as enhanced time efficiency. Various applications and cases are presented: tool and process development and in-line monitoring. For each application, the methodology can be applied with slightly different emphasis. In the case of process development, there may be defect learning that requires separate analysis of defects. Here, using smart sampling and the defect review SEM, the exact nature of the defect can then be determined. For process monitoring, when an excursion is detected, the corrective action can be immediately taken.

A special SRAM has been designed as a yield enhancement vehicle in a 0.35 micrometer CMOS technology. Extra design rules were added to encourage process defects on certain places and discourage them on others. From the failure signature of a memory cell (0 or 1 failure) and its failure extent (single cell, double cell, bitline, wordline, ...) one can uniquely determine the process related cause of the failure. A dedicated test program has been developed to find the most common failures in a memory cell (e.g. floating bitline, bitline shorted to ground or Vdd, shorts between the nodes of the cell, ...). The innovating characteristics of the design allow to link these failures in an SRAM with high probability to a process related defect and its location within the memory cell. By simply testing the SRAM the main cause of failure can be found which can help to drive yield improvement, without doing intensive failure analysis. In this paper the design philosophy and the test methodology of this SRAM are described, illustrated with some examples of process related defects that proved the usefulness and the strength of the design and the test program.

This paper describes some of the methodologies employed to achieve rapid yield learning on 0.25 micrometer, three-layer metal CMOS process. This includes: (1) design of a manufacturing-representative process qualification vehicle which readily lends itself to failure analysis and (2) the tools employed to define and resolve yield-limiting mechanisms in an expeditious manner. Electrical SRAM bitmapping, physical failure analysis and in-line inspection were used to identify and resolve a primary failure mechanism on the 0.25 micrometer, CMOS process. In this instance, small metal landing pads, which are typically used to support stacked contact/via process architectures, were shown to lose adhesion and topple over at various locations within the SRAM circuitry. Further in-process investigations showed that this problem could be modulated and eliminated through changes in the metal deposition temperature. Lowering the metal deposition temperature eliminated this problem and led to improvements in both memory and logic yields.

Automatic defect classification (ADC) on the optical defect detection and review tools have found increasing acceptance in the cleanroom for defect reduction during all phases of yield learning (process R&D, yield ramp and mature production). However at 180 nm technology node, the optical tools are unable to classify the smaller defects of interest. SEM based ADC tools provide this capability through high resolution imaging and classification. This paper will provide an overview of past and future yield learning trends and challenges, role of ADC in the yield learning process and a detailed review of the SEM based ADC tool evaluation project conducted at SEMATECH during 1997/1998 which yielded the following beta results at a SEMATECH member company fab.

Calculation has been carried out on the current responsivity of an Al_xGa_1-xN(n)-GaN(p) photodiode ultraviolet (UV) detector in which the Al_xGa_1-xN layer has an energy band-gap grading (EBGG). The analytical solution to the one- dimensional continuity equation was used in the calculations. The spatial dependence of the material properties, such as energy band-gap and absorption coefficient of the photodiode's n-type layer is included in the solution. The band-gap grading due to a reduced absorption coefficient at the surface region (where recombination occurs) and the built in electric field results in the increase of the minority carrier generation in the vicinity of the junction resulting the enhancement of carrier collection efficiency. Within the range of small values of EBGG there is a substantial rise in the detector responsivity with increasing grading. In the case of surface recombinationless Al_xGa_1-xN(n) front side layer the further increase of the grading does not result the significant rise of responsivity especially in the spectral region near the cutoff. Much more pronounced the increase in responsivity with the grading has been found when the surface recombination was present.

The quasi-static degradation will exhibit identical shifts in parameters for identical total charge injection irrespective of the rate of injection. For this paper, three different injection rates were used to inject same total charge in identical devices. Unequal shift in device parameters for each experiment indicates non-quasi-static nature of degradation. As a result, DC stressing experiments can not be used to accurately predict AC degradation. A novel method of accelerating the stress along frequency dimension is proposed and experimental results are presented. This method can predict AC degradation for any frequency using an empirical model.

Ultra-thin gate oxides grown by rapid thermal processing in N₂O-based oxidation ambients were evaluated. Gate oxide integrity was improved by incorporating more nitrogen in the thin gate oxides and by diluting oxidation ambients in inert gases.

Test wafers were fabricated to evaluate leakage and charge-to- breakdown (Q_bd) of gate oxide capacitor structures subjected to high dose ion implantation. Both insulating and partially conductive (polysilicon) films were present on the wafer backsides during implantation, and the ion implanter's electron flood gun current was varied to optimize the final capacitor leakage yield. Relative to a conductive (polysilicon) backside film present during ion implantation, a backside 1700 Angstrom LPCVD Si₃N₄ layer provided significantly improved gate oxide protection, after optimization of the electron flood gun current. The backside LPCVD Si₃N₄ had no discernible effect on the Q_bd of the capacitors after high dose ion implantation.

High Density Plasma (HDP) process has been predominately used for inter-metal dielectric film due to the superior metal gap fill capability comparing with the common plasma-enhanced CVD process. However, it causes severe hot-carrier (HC) lifetime degradation. Most of works are concentrated on plasma charging damage. The limited study of HDP plasma charging effect on NMOSFET and PMOSFET HC lifetime degradation restricts the understanding of its behavior. Furthermore, the impact of hydrogen related defects on HC lifetime has not been interpreted clear enough to understand the effectiveness of SiN layer. In this research work, the effect of HDP process on NMOSFET and PMOSFET hot carrier lifetime have been systematically studied and investigated. The sensitiveness of HC degradation on plasma charging induced by HDP process on NMOSFET and PMOSFET has been explicated. The behavior of SiN layer on NMOSFET has been studied. The location of SiN layer has been recommended to improve the HC performance.

The detrimental effect of heavy metal contamination on gate oxide reliability has been well documented for oxides thicker than 7 nm. This study offers evidence of the detrimental effect that metallic (Fe, Cu) contamination has on ultra-thin gate oxide reliability. Oxides grown at 850 degrees Celsius of 3.5 and 7 nm thickness were intentionally contaminated with Fe (pre-oxidation) or Cu (pre- and post-oxidation.) Bulk silicon FE concentrations of 5 X 10¹⁰ to 1 X 10¹³ atoms/cm³ were achieved through the spin doping of an aqueous FeCl₃ solution on the wafer surface prior to oxidation. Pre-oxidation Cu contamination was attained through full wafer immersion in a 10:1 HF:H₂O solution contaminated with CuSO₄ of varying Cu concentrations (1 ppb to 100 ppb), while post-oxidation contamination results from a 30 minute 450 degree Celsius forming gas anneal which drives in Cu previously deposited on the backside of the wafer. A new corona-based technique was used to measure the stress-induced leakage current (SILC) characteristics of the contaminated and control oxides after various stress fluences, from 10^-5 to 10^-1 C/cm², in either the Fowler-Nordheim or the direct tunneling regime for the 7 and 3.5 nm oxides respectively. This non-contact technique employing the COCOS (Corona Oxide Characterization of Semiconductor) methodology measures current flowing through the oxide as a function of the oxide electric field induced by corona. In addition, electrical measurements on MOS capacitors were performed and the results compared to COCOS SILC results. For the 7 nm oxides, COCOS measurements clearly showed enhanced SILC due to metallic contamination confirming previous findings. For the 3.5 nm oxides, two distinct features were established: (1) pre-stress I-V characteristics were consistent with a direct tunneling mechanism exhibiting a distinct shift to higher currents at lower electric fields and (2) the SILC was smaller in magnitude than that exhibited by the 7 nm oxides. Existing SILC models (i.e. trap-assisted tunneling) were used to interpret the I-V data. In addition, this stress resulted in oxide wearout, which produced noticeable flat-band shifts and an order of magnitude increase in interface state density, also measured using the COCOS technique. The effect of metallic contamination on these wearout issues was also investigated.

The temperature distribution inside a package is determined by the heat transfer from the package to the ambient, depending on the heat conductivities of the different used materials. With the help of finite element simulations the thermal behavior of the package can be characterized. In precise simulations convection and radiation effects have to be taken into account. In this paper the influence of different materials like the ceramic, the pin and die attach material and adhesive material between the chip and the die attach on the thermal resistance of the ceramic package will be investigated. A finite element model of the ceramic package including a voltage regulator on the chip was created. The simulations were carried out with the finite element program ANSYS. An easy way to take the radiation effect into account, which normally is difficult to handle in the simulation, will be shown. The results of the simulations are verified by infrared measurements. A comparison of the thermal resistance between the best case and worst case for different package materials was done. The thermal conductivity of the ceramic material shows the strongest influence on the thermal resistance.

Wafer-level reliability (WLR) testing is an important tool that is used during the productization phase to investigate the reliability performance of devices and materials before full qualification cycle. The rapid nature of the WLR testing permits the process engineer to evaluate process variation and to obtain almost instantaneous feedback about its reliability impact. Fast reliability feedback is essential to help the process engineer build reliability into our product during the productization phase. Understand the root cause and failure mechanism after WLR testing, failure analysis plays a very important role. This paper describes the fundamental requirements for failure analysis equipment needed, the failure analysis and preparatory techniques used to locate the failure sites and cases study will be presented.

Abnormal IDDQ (Quiescent VDD supply current) indicates the existence of physical damage in a circuit. Using this phenomenon, a CAD-based fault diagnosis technology has been developed to analyze the manufacturing yield of logic LSI. This method to detect the fatal defect fragments in several abnormalities identified with wafer inspection apparatus includes a way to separate various leakage faults, and to define the diagnosis area encircling the abnormal portions. The proposed technique progressively narrows the faulty area by using logic simulation to extract the logic states of the definition area, and by locating test vector related to abnormal IDDQ, following which fundamental diagnosis way employs the comparative operation of each circuit element to determine whether the same logic state with abnormal IDDQ exists in normal logic state or not.

Systematic investigations on defect-free IDDQ in deep sub- micron CMOS with reverse body bias were performed by SPICE simulation to improve resolution of IDDQ measurement. Effects of reverse body bias on off-state leakage of scaled CMOS devices and IDDQ of typical CMOS circuit cells were investigated. It was found that reverse body bias could effectively reduce worst case defect-free IDDQ of typical circuit cells by more than one order in magnitude for technology generation down to 0.18 micrometer. The reduction in worse case defect-free IDDQ is enhanced as the device temperature goes up and diminished as the temperature goes down. Further investigation showed that reverse body bias also made the defect-free IDDQ less sensitive to the input state; therefore one single IDDQ current threshold might still be used for IDDQ testing down to 0.18 micrometer technology generation. It was found that there might exist an optimal reverse body bias that minimizes the defect-free IDDQ current. The optimal reverse bias value decreases as the temperature goes down and might vary from circuit to circuit, process to process, and technology generation to generation.

Liquid crystal method is one of the techniques for failure analysis. This technique is well known way to identify a failure point on a silicon integrated circuit. However, the tendency of LSI devices in recent years towards smaller feature size, higher density, lower electric power and larger chip size has created a demand for improvement of this technique towards higher accuracy and increased reliability of failure point localization. In this case, we developed a new technique for applying the liquid crystal method. With this technique, we improved four aspects of the analysis: (1) Automatic adjustment of the temperature towards the transference point of the liquid crystal by image processing. (2) Automatic display of the 'hot spot' by image processing. (3) Automatic oscillation of the applied voltage for enhanced visibility of the current leakage point. (4) Minute control of the temperature from the reverse side of the package using a Peltier element. As a result of this improvement, we could realize improved accuracy for the liquid crystal analysis and reliability of failure point localization. This thesis reports how this technique can be established as a working technique for routine failure analysis, with a practical detection sensitivity of about 1 (mu) W. This method should be called LCIP (Liquid Crystal with Image Processing method).

The results of laser-semiconductor material interaction are presented. The laser source for these experiments was an UV laser at 0.34 mkm wavelength with 7 ns pulses at 100 Hz repetition rate focused at the spot of 3 mkm diameter, laser fluence was more than 1.1 J/sq cm corresponding to the minimum energy density required to forming kerf. Material of target was p-Si with thermal oxide silicon. We have investigated changes of electrophysical (dynamic and static) performance of diagnostic structures vs. distance between the edge of laser kerf and the edge of diagnostic structures for definition of characteristic zones around the spot of laser - material interaction. The diagnostic structures included p-n junction or source of MOSFET. From the measurement made, back current for p-n junction and transfer characteristic for MOSFET and time carrier storage in source capacity of MOSFET were studied. We have determined the 3 zones around the spot of laser material processing: Zone 1. The electrophysical (dynamic and static) performance of diagnostic structures heavily changed at a distance as small as 4 - 5 mkm. It is bigger than length of region recrystallized material extracted from laser kerf (about 2 mkm). The leakage current increased. The length of zone depends from supply voltage to the diagnostic structures. For example, the length of zone 1 for supply voltage 8 V was 4 - 5 mkm and for supply voltage 20 V - 30 mkm. Zone 2. For distance between the edge of laser kerf and boundary of diagnostic structures larger than 5 mkm, the electrophysical (dynamic and static) performance of diagnostic structures changed, but restored in time. Time of 50 percent restore of electrophysical performance of diagnostic structure was about 408 min. Zone 3. For distance between the edge of laser kerf and boundary of diagnostic structures large than 70 mkm, the free electrons generated by laser irradiation, filled charge traps which began to release after laser material processing. Time of discharge traps was about 408 min. In our experiments we have realized a distance of 5 mkm form the laser kerf to the diagnostic structures and 28 mkm to the working multiplexer circuit.