Sub-0.5 micrometers multilevel metal schemes impose stringent requirements on both gap-fill and planarity of interlevel dielectrics. A variety of novel materials and processes are being investigated to meet these process requirements. In this paper, four dielectrics with good gap- filling capabilities are evaluated for planarity characteristics: SiO₂ deposited using a high density plasma (HDP) with simultaneous deposition and sputtering, an organic spin-on-glass material SOG-A, an inorganic spin-on-glass material SOG-B, and SiO₂ deposited using ozone and TEOS at sub-atmospheric pressure (SACVD). These materials are used for gap-fill followed by a capping layer of PETEOS. For global planarization, only the top layer of PETEOS is planarized using chemical mechanical polishing (CMP) without exposing the underlying gap-fill material. Planarization characteristics of the dielectric stacks are found to be significantly different, both before and after CMP. The CMP throughput is found to be very sensitive to the choice of the dielectric stack. For a given planarity goal, the CMP throughputs of three of the dielectric stacks are found to be significantly higher than that of a conventional single layer interlevel dielectric (ILD) consisting of only PETEOS.

Chemical mechanical planarization (CMP) has been used to fabricate a 0.35 micrometers 16 Meg SRAM with quadruple polysilicon stacks. The use of CMP results in complete planarization of over one micron of topography. CMP planarization results in improved photolithography depth of field when compared to standard resist etchback planarization (REB). Data from a lot processed using CMP at contact dielectric and interlayer dielectric is compared to a lot that was processed using standard REB for planarization.

Multilevel interconnection technology requires higher and higher planarization performances, to allow the use of three or more interconnection layers. A high planarization degree is in fact mandatory to avoid process degradation with the increasing number of interconnection layers. The cold planarization scheme, most widely used nowadays, consists in the SOG (spin on glass) deposition, for gap filling, followed by the SOG partial etch-back (PEB) process to remove SOG from the top of metal structures, where VIAs are to be opened. This type of process is, however, limited by SOG gap filling capability. In this paper a new semi-integrated SOG based inter-metal dielectric (IMD) planarization process is shown, capable of filling metal spaces down to 0.4 micrometers , and providing a good long-range planarization degree. The possibility of extending SOG based planarization processes to .35 micrometers generation devices has been successfully demonstrated with the introduction of an oxide tapering process just before SOG coating. The tapering consists of an argon sputter etch, integrated in the same equipment where the first PECVD oxide deposition is performed. Different argon etch conditions were evaluated to obtain the optimal oxide shape. The planarization process was completed with an integrated partial SOG etch-back and PECVD TEOS cap layer deposition process. Results are presented in terms of SOG filling and planarization degree data as a function of gap width and aspect ratio and in terms of process defectivity.

The relationship between plasma etch chemistry and via resistance has been investigated. A gas mixture of Ar/CF₄/CHF₃ yields lower via resistance than Ar/CF₄. However, decreasing the overetch of the Ar/CF₄ process improves resistance and failure rate. A longer DI water rinse after solvent strip improves via resistance and failure rate by either dissolution of aluminum fluoride, or corrosion of the aluminum under the via lifting out the organometallic polymer. Higher deep UV photostabilization temperature before etch gives a lower via failure rate with tighter distributions. XPS results show that the Ar/CF₄ gas chemistry increases sputtering of aluminum out of the vias during overetch, increasing the amount of aluminum fluoride present, which correlates with the worsened via resistance observed.

To achieve good step coverage for submicron contacts/vias, many approaches have been taken in recent years in VLSI production. While CVD tungsten plug is widely implemented in the U.S. for submicron manufacturing, planarized aluminum plug (i.e., high temperature aluminum deposition) is slowly emerging for its process simplicity and low wafer cost. In this paper, we present the plasma etching studies on the high-temperature-deposited AlSiCu (or hot aluminum) and its application in manufacturing of ULSICs with 0.6 micrometers design rules. The etchability and manufacturability of this high-temperature-deposited AlSiCu have been proven and demonstrated with submicron metal lines. Various aspects of the hot aluminum etching, including profile control, residue, microloading, and resist selectivity, are discussed in detail.

Here we report a new thermal dry etch process for copper using hydrogen peroxide (H₂O₂) and hexafluoroacetylacetone (hfacH). The H₂O₂ oxidizes copper to form either copper(I)oxide or copper(II)oxide depending on the etch temperature followed by removal of the copper oxide by hfacH resulting in formation of volatile copper(bis- hexafluoroacetylacetonate) [Cu(hfac)₂] etch species and water. Copper has been successfully etched by this process at temperatures as low as 150 degree(s)C and etch rates of up to approximately micrometers /min at 190 degree(s)C.

Surface charging effect on microloading has been observed using both undoped and doped polysilicon hard mask for sub-quarter-micron contact etching in a MERIE. Surface charging on the undoped polysilicon mask due to non-uniform plasma has caused severe microloading. However, doped polysilicon mask has been very effective to suppress microloading effect up to 0.1 micrometers , because no charge builds up on the surface of the mask. In case of undoped polysilicon mask, both surface charging and microloading effect could be reduced by either decreasing B-field or increasing pressure and gas flow, which improves plasma uniformity.

Technologies are described which can completely fill contacts, vias and trenches with a PVD or CVD barrier metal film and a PVD Al-Cu plug. The presented processes are demonstrated to be applicable for contacts or vias having sizes down to 0.25 micrometers and aspect ratios of up to 5.

Copper is known to diffuse in dielectrics subjected to high electrical bias at temperatures as low as 100 degree(s)C. Also, it does not adhere to the interlayer dielectrics like SiO₂ and polymers. In addition, copper corrodes readily in the corrosive environments. These properties of copper have inhibited the early acceptance of copper as the interconnection metal in the high performance integrated electronic circuit/devices. We have investigated the use of possible diffusion barrier (DB) and adhesion promoter (AP) materials in the conventional layered structures which lead to an increase in the total interconnection resistance negating the advantages of copper. Also, since the subquarter micron circuits necessitates the need of < 10 nm thick DBAP material, such layered structures are generally not stable under the interconnection processing, chip packaging, and/or actual use conditions. In this paper, we present results of our study of the electrically stable and corrosion resistant doped copper as the interconnection material. Al, Mg, and Ta, all of which have considerably higher free energy of formation for their oxides compared to that for Cu or Si oxides, have been added as the dopant in concentration range of 0.5 - 10 atomic percent in copper. Resistivity, adhesion to dielectric surfaces, effect of annealing to temperatures as high as 800 degree(s)C on such properties, corrosion resistance in air, and I-V/C-V characteristics of the metal/SiO₂/Si capacitors have been investigated. It is found that addition of such dopants provides the necessary passivation. Doped films are very smooth even after anneals to temperatures as high as 800 degree(s)C. They did not lose adherence to SiO₂ substrates after such anneals as demonstrated by the adhesive tape-peel tests. Preliminary indications are that doping has reduced the overall stress in the film. There is a small increase in the resistivity of copper, caused by the addition of these dopants. For example, for Cu with Mg (less than 2 atomic percent) the resistivity remains at or below 2 (mu) (Omega) cm. These results are compared with layered Al/Cu, Mg/Cu, Ti/Cu and TiN/Cu and show that doped films of copper satisfy all the reliability requirements at a small sacrifice of the resistivity in a manner similar to Al containing small amounts of copper.

The use of copper chemical vapor deposition and plasma etch to form interconnects for VLSI circuits have been investigated. Deposition results to date show reliable deposition of copper with bulk-like resistivity and good deposition uniformity. The effect of substrate temperature on deposition was investigated. The issues of precursor consistency and effects of contamination in the delivery system were also addressed. Feasibility of plasma etch has been investigated. Preliminary results show that the use of hard masks and wafer temperature above 160 degree(s)C are necessary. The etch chemistry used is chlorine based, adapted from an aluminum etch process. Results show anisotropic etch with some notching which is currently being addressed in further development efforts.

Contact and via step coverage has always been an issue for aluminum metallization as device geometry continues to shrink. Conventional aluminum sputtering has failed to yield a reasonably good step coverage which is a potential reliability issue. Many efforts have been put in for the past years, which includes CVD tungsten, (both selective and blanket tungsten with etchback) and planarized aluminum to fill sub-micron contacts. The tungsten module requires additional process steps when it is to be integrated into the existing flow. Aluminum plug, on the other hand, is more attractive because of reduced process complexity and wafer cost. In this paper, we describe each module and present a comparison between various aspects of the W-plug, Al-plug and conventional cold aluminum modules. We have demonstrated the manufacturing capability of both W-plug and Al-plug for submicron contact/via process. We have also proven the Al-plug process for Chartered's 0.6 micrometers contact/via technology and believe that the Al-plug process has potential for future 0.5 micrometers contact/via technology.

Increased numerical aperture lenses necessary for imaging smaller features have the trade off of reducing the usable depth of focus (DOF) for larger linewidths in a photolithographic process. Large site focal plane deviations (SFPD) can easily consume the available DOF and severely affect the ability to resolve features. The use of a plasma backside etch of the wafer to remove tungsten residue after tungsten deposition will greatly increase SFPD. This paper demonstrates that a simple hardware retrofit in the CVD tungsten reactor can substantially improve the SFPD and via image quality otherwise degraded by backside etch. This retrofit has improved the imaging of both four metal layer 0.8 micrometers and two metal layer 0.65 micrometers interconnect metallization processes that had experienced localized SFPD problems. This hardware retrofit is easily extendible to greater than four metal layers with no significant effect on SFPD and qualitative post resist develop inspection.

Ultrasonic wirebond pull test failures were identified on 7 of 30 development lots receiving a rapid thermal processed (RTP) titanium nitride (TiN) barrier metal (as part of the metal film stack) over a 16 month period. In some cases, the pull test failures occurred at forces less than the minimum requirement of 2.5 grams. The failures were intermittent in wafer location and resulted in exposed borophosphosilicate glass (BPSG) under the metal pads. No trends were found with product type, process dates or sequence, or processing equipment, (BPSG, metal deposition or RTP). The faulty films did not fail tape peel adhesion tests, and thus could not be identified by that technique. The problem was found to be related to an interaction between the titanium and BPSG during the RTP nitridation process. Our experiments, analytical studies and literary surveys suggest that a dopant in BPSG either embrittles the TiN (or interfacial glass) through consumptive segregation or enhances the BPSG flow properties during RTP, creating a weakly adhering interfacial region after the ultrasonic action of the wirebond process. Further experiments refute the reflowing BPSG theory and somewhat substantiate the dopant segregation/embrittling phase theory.

Aluminum plug process for submicron via filling can be improved by using conventional sputtering machine and multi-step deposition process. It is found that the first-step aluminum deposition greatly impacts via step coverage. The effect of this first step metal thickness is more dramatic at higher deposition temperature. Our experiments show that it is necessary to have a continuous Al film in the vias to fully cover the sidewall and bottom at the early stage of the deposition, so that the bulk material can flow in during deposition to fill the vias. The improved process has been successfully implemented in volume production of 0.6 micrometers ASIC and 0.6 micrometers SRAM technologies.

This paper reports on the results of the optimization of a high throughput sputter etch process prior to interconnect deposition with no device damage, performed on the Endura HP PVD system. The second level metallization for a 2-level metal interconnect scheme requires a pre- metallization sputter etch of the vias in order to remove the native oxide and the fluoro-carbon residues left after the ILD oxide etch. For high throughput processing, high etch rates are required along with the essential prerequisites of plasma processing, namely, good process uniformity and no electrical device damage. A high density dual-frequency system with independent control of plasma and bias powers was used to optimize the pre-metallization etch using the second level of a 256 K SRAM device test structure fabricated in a 150 mm wafer production line. Response surface methodology (RSM) was used to explore the parameter space of the sputter etch process. The rf plasma power, rf bias power and the SiO₂ thickness etched were chosen as the 3 independent variables. The SiO₂ etch rate, SiO₂ etch uniformity, via resistance & uniformity and threshold voltage & uniformity were measured and modeled as the response variables. SiO₂ etch rates from 214 A/min to 926 A/min, SiO₂ etch uniformities from 1.88 to 7.27% 1-sigma, via resistances from 0.32 to 0.42 Ohms, and threshold voltages from 0.74 V were obtained. A suitably wide process window was established with the excellent process/device results and a 40% reduction in process time.

Laser programmed inter-level metal connections have been developed as a means to achieve high density linking for customization in programmable gate arrays and for additive redundancy in restructurable integrated circuits. This work reports on the linking of 4 X 4 micrometers crossings of standard two-level metal interconnect lines and subsequent microstructural analyses aimed at understanding the mechanism of link formation. The links were formed by focusing a laser on metal 1 through an annular region of metal 2. The mechanism of link formation appears to be a physical connection made by a fracture of the inter-level dielectric (ILD) layer due to the stress of thermal expansion of the metallization with molten metal 2 filling the crack. Focussed ion-beam (FIB) cross sectional micrography and finite element analysis (FEA) have allowed us to analyze the successfully formed links as well as the failures to link. As a result of our analysis, we have begun to understand how to optimize the device geometry for very high reliability laser linking.

This paper reports on the dramatically enhanced effect rapid thermal anneal (RTA) treatment has on the aluminum (Al) diffusion barrier integrity of reactively sputtered low density titanium nitride (TiN). This low density as sputtered TiN is shown to be superior to high density as sputtered TiN after both films have undergone an identical RTA treatment. The superior integrity of the low density TiN is attributed to enhanced oxygen gettering during RTA treatment at the Ti/TiN interface. This oxygen gettering has been shown to create a titanium oxynitride (TiON) layer between the Ti and TiN which accounts for the greatly enhanced barrier integrity.

This work introduces a comprehensive analytic model of the sputtering mechanism present in ion beam etching and reactive ion etching processes. Our final objective is to correlate the etch rate to the plasma reactor parameters. Experimental verifications for GaAs etching show a good agreement for ion beam etching. In the case of reactive ion etching, the imperfect agreement is explained by the influence of effects such as flow rate and temperature not taken into account in the theoretical approach. We also present parametric investigations of GaAs etched in SiCl₄ plasma.

Some basic aspects involved in laser micro-machining, like material removal, surface integrity, and dimensional precision, are discussed. Higher surface integrity and lower roughness of the order of submicron can be obtained when both ceramics and metals are machined by an acoustic-optical Q-switched pulse YAG laser. Dimensional precision can be improved by using a focal system with shorter focal depth and by lowering the power density at the focal spot.

As MOSFET dimensions are scaled, innovative techniques are required to overcome many problems specific to short-channel devices, while retaining the performance enhancement that justifies scaling to smaller dimensions. We present a design methodology and an analysis investigating the design approaches and the trade-offs for simultaneously obtaining high performance, reliable, and manufacturable 0.18 micron n-channel MOSFETs. The results of two-dimensional numerical device simulations of three candidate structural approaches that have been selected based on scalability, reliability, manufacturability, and performance considerations are discussed. The influence of effects such as velocity overshoot and inversion layer quantization on the device behavior and the trends and trade-offs are described.

Drain-offset polysilicon thin-film transistors (DO-TFTs) with different offset lengths and doping were fabricated and characterized. The grain boundary trap states in the offset region strongly influence the electrical behavior of the TFTs. The on state current is influenced by the grain microstructure in the drain-offset region and channel region, as evidenced by the drain current activation energy measurements. The off state leakage current is dominated by the generation of carriers in the drain offset depletion region, where the trap states serve as generation/recombination centers and reduce the barrier for tunneling. A model based on the Poole-Frenkel effect and thermionic field emission was developed to account for the leakage mechanism.

A new P-I-N MOSFET structure has been developed with near-intrinsic doping (10¹⁵ - 10¹⁶ cm^-3 in our case) in the channel near the source/drain regions. The new structure is more effective in reducing the peak electric field at the channel/drain junction than LDD structures, and hence results in better hot carrier suppression. Also, the near intrinsic region near the drain reduces the transverse electric field and gives rise to higher carrier mobility and drive current than LDD devices.

As the technology pushes down to half-micron or below, a low flow angle BPSG film for pre- metal dielectric (PMD) becomes necessary. With high BP concentration BPSG, for example 4 X 6, low flow angle can be achieved after proper reflow. The drawback is that, frequently, BPSG crystal appears at smaller poly spacing. The combined sub-atmosphere chemical vapor deposition (SACVD) and BPSG films through in-situ deposition in applied materials P-5000D system was implemented to not only improve reflow angle but also suppress the crystal formation at any poly space. A crystal-free with 11 degree(s) flow angle PMD was achieved by using 4KA SACVD and 5KA BPSG over 6000A poly lines. A detailed SACVD/BPSG process and the comparison of BPSG reflow characterization with and without SACVD are presented.

Much work has been performed in the past few years on N₂O oxidation as a method to produce nitrided gate dielectrics. Most of this work has centered on processes in horizontal or vertical batch furnaces operating at atmospheric pressure. Obtaining good oxide thickness uniformity, both within the wafer and across the batch, has proven to be more difficult for N₂O oxidation than for O₂ oxidation. As the gate dielectric thickness requirement approaches 50 angstrom or less, uniformity of the dielectric thickness becomes more critical. For thinner oxides, single wafer rapid thermal oxidation (RTO) may be the only feasible oxidation technique. N₂O oxidation development in an integrated gate stack cluster tool has been underway for more than one year. This oxidation has been performed under a variety of process conditions on both conventional silicon and SOI wafers. Recent results indicate that oxides grown in N₂O at lower pressures (approximately 100 Torr) have better electrical characteristics and thickness uniformity than oxides grown in N₂O at atmospheric pressure. Reliability test indicate that oxides grown in N₂O have consistently better breakdown field, charge to breakdown, and time dependent dielectric breakdown than oxides grown in O₂ under identical conditions; however, unstressed N₂O oxides have higher interface trap densities than similar O₂ oxides.

Ultrathin (< 5 nm) dielectric films have been grown on (100) silicon using rapid thermal processing (RTP) in a nitric oxide (NO) ambient. The chemical composition was studied using x-ray photoelectron spectroscopy (XPS). Interface state density, charge trapping properties, and interface state generation during Fowler-Nordheim electron injection have also been investigated. The films grown in NO have excellent electrical properties. These properties are explained in terms of much stronger and large numbers of Si-N bonds in both the bulk of the dielectric films an in Si-SiO₂ interface region.

Indications are that very thin dielectrics needed for future generation of integrated circuits will be in a form of nitrogen-modified oxide. A significant amount of experimental data on growth kinetics for oxides grown/nitrided in N₂O has been gathered. It appears that nitrogen neutralizes growth sites at the oxide-silicon interface, which significantly slows down the oxidation process when N₂O is used as an oxidizing ambient. In this paper, the classic Deal-Grove formulation is extended to include the concentration of the growth sites. Also, the continuity equation applied to the growth sites is used to determine the concentration of the growth sites. This model has been incorporated into a TMA SUPREM-3 process simulator, and the model parameters calibrated with available experimental data. This provides not only the tool needed for process simulation, but also a better understanding of nitrogen modified oxide films.

A high quality and UV-transparent plasma enhanced chemical vapor deposition (PECVD) silicon nitride film is well developed to form a passivation layer for non-volatile memory devices. The dependence of the film properties on process parameters has been studied by factorial designed experiments. The deposition rate, uniformity, stress, refractive index, wet etching rate, density, step coverage, and UV-transmittance are the items used to evaluate the film properties. Rutherfold backside scattering (RBS) and hydrogen forward scattering (HFS) are used to measure the film composition and total hydrogen composition, respectively. Compared to the traditional PECVD nitride (PE-SiN) film known to have tensile stress and opacity to ultra-violet light (UV light), the developed PE-SiN film with very low compressive stress (< 1E9 dynes/cm*2) and excellent UV-transmittance (> 70% for 1.6 micrometers - thick film) can be achieved. The developed film has higher density, lower hydrogen content, and high N/Si inside film. Based on RBS/HFS, UV-transmittance and Fourier transform infrared spectrum (FTIR) results, the material and optical properties of the developed PE-SiN film are well investigated. This developed PE-SiN film is successfully applied to EPROM devices, and very good electrical and reliability performances have been demonstrated.

A method of producing submicron (hundreds of nanometers and less) periodical structures on the solid state surface by means of one-pulse laser radiation treatment is developed. The resulting structures look like a system of narrow parallel equidistant grooves. Before a treatment the surface may be covered by one of several thin layers to be destroyed. It is possible to obtain the grooves, a width of which is from 10 to 100 times less than the wavelength of used laser radiation. It is possible to vary the distance between the grooves in a wide range. When a carbon dioxide TEA-laser (0.2 joule-energy, 10.6 micron-wavelength) was used for the treatment of samples (800 angstrom-aluminum film evaporated on the optical glass plates) periodical structures looking like a system of narrow parallel equidistant grooves were produced on an area with a diameter of about 2 mm. The width of the grooves was less than 0.3 micron and a distance between the grooves varied from 7 to 500 microns. Therefore this method has enabled us to obtain grooves with a width about 30 times less than the wavelength of the laser radiation used.

The present paper contains theoretical investigation or the possibili iy 'oritr:'1i1n, the impurity concentration distribution iribLue ci JI!t £1e1.d—rrn u t,iit tLL.it1L(Jfl equin is aen into account . The Three , acting on impar ty atoms , results roii the temperature gradient or the crystalline lattice. The expression ror heat or transport Is obtained rrorn rnicroscopc theory. Calculations ror concrete impurities show that concentration of impurities near maximum temperature can either increase (0, In, Sb) or decrease (B, P3 C) , deieni.rig on the erfeotive S1ZCS 01° the impurity atois and on their interaction With crystal lattice. Calculation UP B and Sb Iflipurities ifl • SiliCOfl at Ufliroflhl fld equal their initial concentration IS perrorned. Redistribution or these impurltles arter temperature 1eld With maximal temperature at the crystal sarrce 1s appli ed resui ts In creation or p—n junction near the surrace. Similarly, the p—n—p structure ifl volume of the crystal is created w:er tb temperature maximum is located there . Strongly absorbed laser radiation can be used to reach appropriate temperature gradient near the surrace.

A new technique for low temperature CVD TiN is introduced as a barrier/glue layer for sub 0.5 micron applications. Excellent conformity (> 70%) is achieved while maintaining good electrical performance and reliability. The films are shown to be polycrystalline TiN with no preferred grain orientation. In addition compositional analysis shows significant amounts of carbon in the film presumably between the grains. The electrical properties of the CVD film were evaluated at the via and contact level. The contact and via resistances of tungsten plugs using CVD TiN glue layers are shown to be comparable to plugs using sputtered TiN. The barrier performance of the film was also evaluated at the contact level. The superior junction leakage data indicate that the CVD TiN film should have wide application as a barrier metal for sub 0.5 mm applications.