This PDF file contains the front matter associated with SPIE Proceedings Volume 12325, including the Title Page, Copyright information, Table of Contents, and Conference Committee lists.

Source-mask optimization and EUV mask structure optimization are studied to maximize DOF and NILS for honeycomb hole arrays at 0.55NA. Optimization flow on mask structure conditions for good and stable NILS performance, such as peak-NILS, NILS-DOF, and NILS-MEEF, is proposed to minimize the local CD variation as a result of EUV mask properties. Using NILS metrics, the absorber thickness and the mask CD with optimized illumination conditions are determined for the maximum performance, together with the tolerance of absorber thickness and mask CD. EUV binary absorbers using high-n/mid-k and low-n/high-k materials, and EUV PSM absorbers using low-n/low-k and highreflectance materials, are compared for 28-, 26-, and 24-nm honeycomb hole arrays.

Nano-imprint lithography (NIL) has unique features, including the ability to design at a resolution of 1x nm and three dimensional patterning. Although productivity was a concern for NIL, improvement has been made with recent technologies such as multi-field imprint and spin-coating resist. However, the environment surrounding the semiconductor industry is changing. One of the biggest waves is “carbon neutrality,” and it is believed that energy-saving technologies will be important for the future of the semiconductor industry. In this study, we evaluate the current performance of NIL and its future prospects as an energy-saving technology that will help the world achieve carbon neutrality by 2050.

Imprint lithography is an effective and well-known technique for replication of nano-scale features. Nanoimprint lithography (NIL) manufacturing equipment utilizes a patterning technology that involves the field-by-field deposition and exposure of a low viscosity resist deposited by jetting technology onto the substrate. The patterned mask is lowered into the fluid which then quickly flows into the relief patterns in the mask by capillary action. Following this filling step, the resist is crosslinked under UV radiation, and then the mask is removed, leaving a patterned resist on the substrate. The technology faithfully reproduces patterns with a higher resolution and greater uniformity compared to those produced by photolithography equipment. Additionally, as this technology does not require an array of wide-diameter lenses and the expensive light sources necessary for advanced photolithography equipment, NIL equipment achieves a simpler, more compact design, allowing for multiple units to be clustered together for increased productivity. Previous studies have demonstrated NIL resolution better than 10nm, making the technology suitable for the printing of several generations of critical memory levels with a single mask. In addition, resist is applied only where necessary, thereby eliminating material waste. Given that there are no complicated optics in the imprint system, the reduction in the cost of the tool, when combined with simple single level processing and zero waste leads to a cost model that is very compelling for semiconductor memory applications. In this review paper, we touch on the markets that can be addressed with NIL and also describe the efforts to further improve NIL performance. In addition, we describe recent efforts to develop pattern transfer processes that can be used to address edge placement error. As a final topic, we describe Canon’s efforts in developing a sustainable future and touch on how new methods can be applied to reduce waste and enable environmentally friendly solutions.

This conference presentation was prepared for Photomask Japan 2022: XXVIII Symposium on Photomask and Next-Generation Lithography Mask Technology, 2022.

The common process window of EUV patterning is being limited when the 1-dimensional (1D) pitch shrinks to 32nm or below. There are many investigations and studies that propose an alternative EUV photomask absorber to mitigate photomask 3-dimensional (3D) topology effects and can partially mitigate the contrast fading effect and reduce through pitch best focus shift.^1,2,3 Another method to counter photomask 3D effects, is sub-resolution assistant features (SRAFs). SRAF insertion is one possible way to create a dense optical environment, which will prevent strong best focus shift from semi-isolated to isolated features. However, the side effect of SRAF insertion is unwanted SRAF printing occurring on the surface or bottom of the photoresist.⁴ In order to predict the partial removal or small residues of photoresist after the lithographic development process, a flow of compact photoresist 3D modeling (R3D) in conjunction with stochastic modeling can be adopted. In this paper, a bright field EUV photomask with regular 1D line-space grid design and positive tone development (PTD) are considered. The SEM images of through pitch 1D structures with various sizes of SRAFs are collected. To quantify SRAF printing, pixel brightness is compared to resist-opened background area, the printing SRAF regions can then be identified and clustered. Compact resist stochastic modeling is also performed by line-width roughness (LWR) sampling and used to predict SRAFs printing pixels by using Average Printing Area (APA) method with R3D modeling.⁵ Therefore, not only severe SRAF printing events can be predicted well, but also the accurate prediction of SRAF printing with very low probabilities can also be achieved.

Advances in chip manufacturing processes continue to increase the number of vertices to deal with in Optical Proximity Correction (OPC) and Mask Data Preparation (MDP). In order to manage the processing time, OPC in sub-nanometer now requires employing tens of thousands of CPU cores. A slight mishap can force the job to be re-run. Increased complexity in the computing environment, along with the length of time a job spends in it, makes a job more susceptible to various sources of failures, while the re-run penalty is also growing with the design complexity. Checkpointing is a technique that saves the state of a system that continuously transitions to another state. The purpose of creating a checkpoint for a job is to make it possible to restart an interrupted job from the saved state at a later time. With checkpointing, if a running job encounters termination before its normal completion, be it due to a hardware failure or a human intervention to make resources available for an urgent job, it can resume from the checkpoint closest to the point of termination and continue to its completion. Checkpointing applications can include 1) resume flow where a terminated job can be resumed from the point close to the termination, 2) repair flow to fix OPC hotspot areas without having to process the entire chip and 3) cloud usage where job migration may be necessary. In this paper, we study the runtime and storage impact with checkpointing and demonstrate virtually no runtime impact and very minimal increase in filer storage. Furthermore, we show how checkpointing can significantly reduce runtime in OPC hotspot repair applications

For the era of multi-beam mask writer, in the 2019 BACUS conference, we proposed the formation of a data format working group to address the need for curvilinear data representation. The new working group was formed in October 2019 driven by major semiconductor companies with representations from Mentor, Synopsys, Nippon Control Systems, D2S, Aselta, and ASML-BRION with the initial goals to quantify the curvilinear data volume problem; develop, test and implement new or revised formats based on OASIS; and to formalize the working group as a SEMI task force (TF). In this paper, the necessity of a new curvilinear data format and the progress of our TF will be introduced. Furthermore, we demonstrate that given the nature of curvilinear data, representing it using native curve formats has significant value to reduce file size for future mask making flows.

With the emergence of complex ILT (Inverse Lithography Technology) and multi-beam mask writers, comes the rise of curvilinear masks. Curvy shapes or all angle piecewise linear polygons provide optimal results for chip makers as it provides larger process windows. For mask manufacturers, the objective remains the same; writing a mask that meets the chip makers’ specifications. However, if the curvilinear shapes need biasing to correct for process effects, then individual edge adjustment is not an appropriate solution as the segment lengths are extremely small. This approach would require far more computational resources then it would for the typical Manhattanized layout. Thus, as the industry transitions from traditional layouts with rectilinear polygons to full curvy, or even a hybrid mix, there must be an optimized path available that enables a more ‘holistic’ approach to correction for all types. One that can balance ease-of-use, data complexity, and robust enough to meet strict tolerances and EPE specifications. In this paper, we will outline a fully supported MDP flow for curvilinear masks. The functionality is provided by the Proteus Curvilinear OPC engine and fully supports ILT and EUV layers as well as other curvilinear masks. We will provide an overview of the data path, from correction to multi-beam writer format. We will also describe the controls necessary to achieve optimal quality and share both data metrics and performance results.

With the use of Inverse Lithography techniques (ILT) becoming more relevant for advanced mask lithography, layouts that rely heavily on curvilinear patterns are increasingly more prevalent. Aside from the substantial increase in data volume, the error budgets in the manufacturing of the smallest printed features have decreased considerably and proximity effects once relegated to noise are now in need of careful correction. The correction of these curvilinear masks must be preceded a mask model and, therefore, it is key to procure a fast and accurate method for predicting the mask distortions. In order to meet this challenge, Synopsys has drawn from its related experience in the OPC space to offer a modeling tool that goes beyond the traditional metrology CD-based methodology by relying on the information along the entire edge of the mask shapes. This contour-based approach is complemented with an Advanced Regression step that provides an additional level of optimization of the model parameters and can substantially improve its prediction accuracy. The result is a practical and precise mask modeling tool with a high level of automation. This paper demonstrates the capabilities of this mask modeling solution to a sample of curvilinear and advanced Manhattan layouts.

We propose freeze cleaning as a method of photomask cleaning in which particles small enough to be embedded in the region less than 100 nm from the substrate surface, where there is virtually no fluid flow, are selectively removed without causing pattern collapse. In freeze cleaning, a high particle removal efficiency is achieved by repeating the sequence of liquid (deionized water) being poured onto the substrate, freezing, and thawing (rinsing) multiple times. Based on the mechanism of particle removal, the timings at which the water freezes, ice growth, and freezing of the entire surface are important parameters that govern freeze cleaning performance. In contrast, when these timings were monitored during repeated processing, a maximum variation of about 16% was observed. The most significant cause of these fluctuations is attributed to the process performed in a system that is open to the atmosphere at room temperature, despite the use of cryogenic N2 at -120°C. Even with these timing fluctuations, by developing and applying an algorithm that monitors individual changes and automatically determines step switching using this monitor information, it is possible to construct a stable and highly efficient processing system without any tool modification.

It is well known that with the development of advanced semiconductor technology, the phase shift mask (PSM) has been widely utilized in the semiconductor lithography process. Usually, the PSM blank coated with negative chemically amplified resist (NCAR) was used for fabrication of AA (Active area) layer and Poly layer mask which utilized in the logic semiconductor products. Under the electron beam (EB) writing systems, this NCAR resist showed better opaque pattern forming ability for complex OPC pattern and sub-resolution assist bar features[1]. In this contribution, a kind of defect so-called tiny MoSi defect that was captured by KLA inspection tool during NCAR mask fabrication process would be described. This kind of defect randomly scattered over the whole mask and located on quartz surface where photo resist was developed for not exposure by electron beam and Cr/MoSi was removed after dry etching process. In order to figure out this problem, we investigated the root cause of tiny MoSi defect by split condition test and cross validation, especially focused on the interaction between each process unit. According to the verification result, we would propose the possible formation mechanism and modify the recipe based on this understanding. The long-term inspection monitoring result showed that this kind defect density could be reduced from two hundred to less than twenty counts after recipe optimization.

As semiconductor device design shrinks, technology requirement for wafer pattern resolution is getting more severe. Requirement for mask pattern resolution is also getting severer due to increase in complexity of mask pattern design. Mask pattern resolution is mainly determined by resist pattern resolution, and adhesion work is known as one of the factors that affects resist resolution. In this paper, the impact of adhesion work on mask resolution was investigated for various hard mask layer (HM). Adhesion work of Ta-base HM is better than Si and Cr-base HM, and resist line resolution on Ta-base HM is better than Si and Cr-base HM. Therefore, ArF attenuated phase shift mask blanks with thin Ta and Ta/Si HM were developed. Line edge roughness (LER) of thin Ta and Ta/Si HM are almost the same as Si-base HM. On the other hand, etching bias uniformity and final line resolution of Ta/Si HM are better than thin Ta HM. Final line resolution of Ta/Si HM is better than Si-base HM. Final space resolution of Ta/Si HM was improved to the same level as Si-base HM with adjustment of HM etching recipe. These evaluation results indicate that the new Ta/Si HM can be a strong candidate capable of enhancing mask resolution on advanced masks for both logic and memory devices.

In this paper we introduce a method of combining the use of the KLA FlashScan® reticle blank defect inspection system and the KLA LMS IPRO reticle pattern registration metrology system for high-precision mask defect inspection and registration. We investigated EUV mask blanks at various production stages and confirmed the reliable measurement of defect coordinates, which propagate through the multilayer stack towards the surface as well as after the absorber deposition process. During the inspection, in addition to the categorization among various types and sizes of blank defects, unique alignment marks were also placed on the mask. These alignment marks allowed us to use a defined coordinate system, enabling reliable and accurate registration of the defect location even on blank substrates. If the mask shop requires EUV defect coordinates in their own internal coordinate system, matching between the mask shop and blank coordinate systems is achieved by measuring both alignment mark pairs and applying the appropriate coordinate transformation. The combined use of inspection and metrology systems proved to be a cost-effective solution for the development of a defect mitigation strategy with automatic workflow for EUV mask shops and mask blank suppliers.

Experimental data, and optical calculations, are presented for the impact of Ruthenium and Diamond-Like Carbon (DLC) capping layers on the EUV reflectivity (EUVR) of Mo/Si multilayers. The multilayers and Ruthenium are deposited by secondary ion beam deposition, while the DLC is deposited by Pulsed Filtered Cathodic Arc. In both cases, the optimal capping layer thickness is shown to be ~ 2.5nm, providing the smallest degradation from the baseline multilayer reflectivity. 2.5nm Ruthenium is demonstrated to result in a drop of 1.8% reflectivity relative to the bare multilayer. In contrast, 2.5nm of DLC results in a drop of only 0.6%, so 1.2% improvement over the typical Ruthenium cap. Optical calculations support the qualitative features of the experimental data, with closer matching when realistic interlayers (1.5nm RuSi or 0.5nm C/Si) and realistic oxide layers (0.6nm RuO2) are included.

The eBeam Initiative completed its 10th annual opinion survey in July 2021 with anonymous feedback from industry luminaries representing 44 companies from across the semiconductor ecosystem – including photomasks, electronic design automation (EDA), chip design, equipment, materials, manufacturing and research. Started in 2012, the Luminaries survey is used each year to gather predictions of industry trends. The optimism for overall photomask market growth captured in the 2020 survey continued to increase in the 2021 survey. 72 percent of survey respondents predict that mask revenues in 2021 will increase compared to 2020 revenues, while 74 percent believe that EUV will contribute to mask revenue growth. EUV also remains the top reason cited by respondents for purchasing multi-beam mask writers. 90 percent of respondents believe that purchases of multi-beam mask writers will grow over the next three years, while purchasing sentiment for laser mask writers and variable shaped beam (VSB) eBeam mask writers has increased compared to last year’s survey. Confidence in curvilinear mask making is also high according to a new survey question, with 71 percent indicating that leading-edge mask shops can handle at least a limited number of such masks. Taken together, the survey results reflect optimism for both business growth and technology adoption in the photomask market.

In 2019, Lasertec successfully developed ACTISTM, the world’s first actinic patterned mask inspection (APMI) system, and has since been providing it as a solution to customers for use in EUV lithography production processes. APMI, is a type of inspection that utilizes the same 13.5nm EUV light used in EUV lithography. ACTIS can perform high-resolution, high-throughput inspection of EUV photomasks and detect all types of printable defects, the mask defects that would be printed on wafers in the EUV lithography process. DUV inspection can detect some of the printable defects. However, DUV inspection cannot detect phase defects, whereas APMI can. A comparison between the inspection performance of DUV and APMI for several defects, including phase defects, is provided in this paper. High-NA lithography is expected to be used for the EUV process at the technology nodes of N3 and beyond. High-NA lithography will be achieved by utilizing anamorphic optics, where magnification scales of projection differ along the horizontal and vertical axes. ACTIS has the extendibility to meet the requirements of high-NA lithography as it can be modified to have the NA on the mask extended along a single axis. Lasertec will develop a new generation ACTIS for use in high NA EUV lithography with higher NA projection optics. Discussions on increasing the NA of projection optics give rise to questions about inspection resolution due to light being blocked by the absorber on the EUV photomask. This paper will discuss this question using the results of simulations at varying absorber heights and NA values.

The Laser-assisted Discharge-produced Plasma (LDP) EUV source has been developed as a light source for actinic mask inspection and beamline application and deployed in the field. LDP EUV source enables to generate high brightness with relatively larger EUV plasma by discharged plasma triggered by laser on one electrode disc which is coated by tin film. As EUVL process is used more in mass-production process, the requirement for EUV source for mask inspection is required more. USHIO LDP source has overcome various issues specialized from LDP source and realized high reliability 24/7 based operation with high brightness maintained. In this session, the following items will be presented. (1) LDP EUV source configuration and operation sequence. (2) LDP EUV source key performance (3) Reliability improvement items. (4) High Brightness Development

Photomask pattern has been traditionally evaluated with limited gauges with 1D cut-line based measurement method on SEM (Scanning Electron Microscopy) image. After the advent of EUV lithography and multi-beam mask writer for curvilinear design, the demand of controlling pattern dimension with higher precision grows in the photomask fabrication. In order to achieve better dimension control, advanced MPC (Mask Process Correction) is applied to the photomask fabrication, and the calibration of the mask process model for the correction is essential technique. For this model calibration, it is necessary to evaluate the pattern dimension not only in limited points but also in a variety of photomask patterns including 1D pattern and 2D pattern such as corner, tip and small jogs etc. After applying MPC, monitoring critical pattern with massive sampling points is also expected to maintain stable photomask fabrication. D2DB (Die to Database) is effective method to evaluate various patterns by comparing SEM images and its layout data which can be used to define POIs (Point of Interests) and to select measurement method automatically, and it realizes massive measurement. D2DB has been widely used to collect massive pattern data printed on wafer. These data are useful to correct OPC (Optical Proximity Correction), optimize wafer process condition, and monitor hotspot, and has made a significant contribution for faster ramp up and yield enhancement. Although the application of off-line D2DB to photomask pattern has been reported, D2DB has a high computational cost, so further performance improvement in terms of throughput is necessary for the evaluation of photomask pattern with higher precision which will be required in near future. In this study, D2DB system for massive measurement of photomask pattern has been developed using the technology cultivated for evaluation of printed pattern on wafer. Images are acquired by CD-SEM and aligned to the layout data. POIs and measurement method are automatically determined and selected by analyzing layout data, and the measurement is distributed among multiple processing servers and performed inline. The obtained massive data is effectively classified by utilizing layout data and quantitative analysis of statistical photomask pattern fidelity is realized. This system enables much faster TAT from measurement to analysis compared to conventional method. Furthermore, the expected effect of consistent analysis through semiconductor manufacturing which is achieved by applying the same D2DB to photomask pattern and printed pattern on wafer is discussed.

Pattern dimension of photomask for flat panel display (FPD) is becoming finer year by year, and it can be seen the movement to use phase shift mask in the critical layer to improve the transfer performance to the panel. For example, transferring small contact holes with high accuracy, a high-transmission phase shift mask capable of obtaining stronger phase shift effect may be required. Currently, we are developing high-transmission phase shift mask blanks for i-line exposure using silicide-based material, and we determined stable manufacturing conditions by investigating the relationship between amount of film-forming process gas and optical properties such as refractive index n and extinction coefficient k. In addition, we confirmed that the cross-sectional shape of this new silicide phase shift film is good, and it can be formed uniformly on large substrate. In this paper, we will introduce the current development status of new silicide phase shift film and the differences from MoSi phase shift film. Moreover, we will introduce high-precision Cr-Binary film suitable for this new silicide film as well.

Recent developments in multi-beam mask writers (MBMW)1 enable the manufacturing of curvilinear masks. This promises higher patterning accuracy on wafer. The increased patterning flexibility takes us into new territories for mask manufacturing accuracy, precision and Mask Rule Check (MRC). MBMW allows Optical Proximity Correction (OPC) to venture into Inverse Lithography Technology (ILT) solutions, enabling accurate curvilinear masks. New challenges are also encountered when building OPC models that target ILT masks, such as on wafer metrology and pattern coverage. This exploration will be the focus of this study, in particular the MRC and mask characterization aspects, leveraging a new curvilinear reticle available at imec. As a result of its fully curvilinear nature, conventional mask metrology – solely based on cutline CDs – is no longer entirely adequate. Therefore, a new metrology flow must be developed to assess and quantify mask errors, relying on mask SEM image contour extraction and Mask Edge Placement Error (MEPE) evaluations. Our proposed flow has three steps: -Mask CDSEM images are loaded into a software, which enables an accurate contour extraction and alignment to the original design. The output of this exercise is a design file with open contours. - The output design file is converted into polygons (i.e., defining inside/outside polygons areas) by utilizing the original design as a guide. This allows for full compatibility with the next stage. -Lastly, a highly-sampled MEPE is determined for all polygons, both from the main and assisting features. The result is then analyzed offline. Ultimately, this curvilinear mask data analysis sequence was used on several subsets of the mask metrology dataset. In order to validate the approach, we reproduced the CD based metrology provided by the mask shop. We then expanded our scope to parametric curvilinear features, to find correlators (i.e. local design properties) to the observed mask error observed (e.g., polygon local curvature or density). Finally, ILT clips were used to verify the determined correlators.

High-NA EUV technology enables cost-effective patterning below the 5nm node. The integration is simpler but still requires multiple innovations. Thinner resists are needed for single-patterning enablement. The decrease in thickness poses a challenge for traditional metrology and inspection systems like OCD or CD-SEM, which lose sensitivity due to diminishing interaction volume. The reverse is true for Scanning Probe Microscopy, which excels in the low-height patterning regime. Here we discuss patterning metrology and introduce defect inspection / review applications for High-NA EUV patterning using a high-throughput SPM.

In this work we describe a new simulation-based verification technology that delivers improvement in verification capability for model-based MPC. This technology incorporates the same physics-based process model that is used in the model-based MPC. The input for this simulation-based verification is the target design, the MPC corrected design, and the mask process model parameters that were used for the correction. Verification is accomplished by performing a simulation that applies the process model to the corrected design, thereby predicting the contours on the mask after exposure and processing using the corrected design. This predicted lithographic result, i.e., the predicted design representation on the mask, is then compared to the target design. Differences are analyzed relative to a user-defined tolerance and, if in violation, are subsequently flagged with the option of being classified in user-defined categories. This new verification technology can also be used to analyze critical regions of the design (“hotspots”) defined by the user, enabling a more design-specific analysis. Note that the simulation algorithm is essentially different from the correction algorithm, so that potential algorithmic issues of the MPC correction are captured by the verification.

MBM-2000, the latest multi-beam mask writer of Nuflare Technology, Inc. (NFT), have achieved reasonable writing time in mask fabrication of 3nm semiconductor technology node, which demand small curvilinear patterns in EUV masks and curvilinear OPC patterns in optical masks. For less line edge roughness and better pattern fidelity, however, the demand of lower dose sensitivity resists keeps increasing. In such a situation, the beam exposure time can be the main bottleneck of the writing time. In order to meet the demand, NFT has developed MBM-2000PLUS, which achieved high beam current density of beamlets ×1.3 larger than MBM-2000. As the result, the writing time became constant up to 170 μC/cm² exposure dose condition without confinement by beam exposure time. Even at the region of exposure dose confinement, the writing time became 20% less than MBM-2000 at 200 μC/cm2 dose condition. In addition, charge effect reduction (CER), which is an electron optics system reducing resist charge effect, has been upgraded from MBM-2000 for improving image placement accuracy. Furthermore, MBM-2000PLUS inherits pixel level dose correction (PLDC) function from MBM-2000 as the solution for less edge placement error and better pattern fidelity. In this paper, those features of MBM- 2000PLUS are highlighted including improvement of pattern fidelity by PLDC function. In order to verify PLDC, a new methodology of quantitative evaluation of pattern fidelity using sine-shape pattern is introduced.

In this study, performance improvement of an i-line laser writer used in the manufacture of masks for photonic device applications was successfully achieved and demonstrated. This was accomplished by conducting a thorough investigation and analysis of key lithographic performance characteristics, enabling the identification of optimal exposure strategies. Subsequent process characterization and design calibration was then performed using software tools. To assess improvement, a side-by-side comparison of performance was made between two identical silicon nitride photonic devices: one fabricated by a mask made using the improved laser writer process, the other by a mask written using a variable shaped electron beam writer. These devices were compared for optical loss to assess mask performance. This study demonstrates that the improved laser writer process enables the production of masks capable of infrared silicon nitride photonic device manufacture. This presents an opportunity in reducing the mask manufacturing costs involved in the fabrication of photonic devices.

Source and mask optimization (SMO) should be applied in extreme ultraviolet lithography (EUVL) for 7-3 nm technology node. Ineluctable wavefront error (WFE) coming from projection optics or 3D mask effect is considered as a single field point effect instead of full field aware in traditional SMO flow. For getting more qualified SMO, a model of full-field wavefront error aware source and mask optimization (FFSMO) is invented. This method focuses on the tradeoff of lithographic imaging at different typical field point as a multi-objective problem. A new multi-objective cost function is established to improve the uniformity of pattern fidelity at different field point. Simulation results show that the proposed FFSMO method has better imaging uniformity at different field points than non-wavefront error aware SMO (SMO-Ideal) or single field point aware SMO (SMO-F2). For line and space pattern at 7nm node, the standard deviation of pattern error (PAE) reduced from 185.0 to 79.2 comparing with the single field point aware SMO. It is demonstrated that the effectiveness of this FFSMO model in terms of balancing and improving imaging uniformity and PW across full exposure field. For contact hole pattern, the standard deviation of pattern error (PAE) reduced from 233.7 to 75.6 comparing with the single field point aware SMO.

Extreme ultraviolet (EUV) reticle incorporated with a pellicle has been widely used for worldwide EUV mask cores. The EUV reticle is typically stored in an EUV inner pod (EIP), in which the EUV pellicle is served to prevent particle contamination. The pellicle is easily deformed due to its structural weakness, thereby altering its transmission as well as impacting the yield of EUV fabrication. Since the mechanical stress induced by external forces in the EUV pellicle is compressively studied, the exploration of stress altered by the air flow through the pellicle frame and/or the inner topography of the EIP is relatively less studied. Here, we present a numerical simulation approach to elucidate the above issue. The derived pressure acting on the pellicle was significantly modulated by the flow conductance of pellicle frame. A air permeability of 90% lead the induced pellicle stress relatively less than the 10% permeability. It suggested that a higher air permeability of pellicle frame could stabilize the air flow between the inside and outside air domains of pellicle more than that using a lower air permeability. We further compared the pellicle stresses derived from the experiment and calculation during the pumping event (from atmosphere pressure to 5 Pa). Results showed a good agreement between the two models. Together, our study indicates that the mechanical stress with air flow through the pellicle frame may dominate the deflection of EUV pellicle in vacuum and the relevant improvement should be considered accordingly.

Mask metrology is a key signoff step in photomask manufacturing process. The challenges for mask makers today are issues revolving around reliably measuring CD (Critical Dimensions) of features on device patterns and mask registration, as the complexity of the patterns increase. These challenges continue to grow on due to the increasing complexity of mask design and the shrinking dimensions of critical features. The CDs are typically measured by scanning electron microscope (CD-SEM). Registration deals with the accurate placement of features on the mask, this paper has a primary focus on mask metrology. To support the mask metrology needs mentioned above, CATS® worked with HOLON to generate an offline CDSEM recipe in both GUI/non-GUI mode for automatic measurement. This implementation leads to the customer being able to automate the process of metrology to effectively use CATS® with the HOLON ZX tool. CATS® integration allows for exhaustive tool commands that can be preset in the CATS® setup file to generate CDSEM recipe. CATS® validates the recipe generation to optimize ZX productivity. To support this flow, here is the outline and the necessary building blocks: - CATS® reads the Mask data (VSB, MEBES, JEOL) job deck with the device patterns, along with metrology locations (Measurements point file) to place the desired marks. - The setup (Job deck and Marks) can be saved as a CATS® Internal job deck format for better efficiency. - The flow terminates with the WRITEFILE step, translating the CATS® Job deck to Machine format files that are needed for automatic measurement on the Holon Tool (CSV file, OASIS, Bitmap files as per specification).

Deep-ultraviolet (DUV) laser writer ALTA4700DP upgraded from ALTA4700. The new design laser mask pattern generator (LMPGs), advance electronic design automation (EDA), and multi-core CPU server (up to hundreds of core) are all constructed on the machine. The effective of machine (exposure time) and CD performance (uniformity, thr-pitch and corner rounding) of products are obvious reduced and improved, respectively. In research, not only the CD performance of mask was obtained by CD-SEM but also the CD performance of wafer was defined by AIMS simulation. The effect of corner rounding was proved by average CD and exposure intensity of contact structure by both CD-SEM measurement and AIMS simulation.

Mask Data Preparation, MDP contains comprehensive contents such as reticle layout, mask fracturing, manufacture rule check, etc. We have demonstrated a MDP application on KLA DB inspection. In order to calculate the rendering compensation, Pre-Swath Calibration, PSC is performed before DB inspection. We have built a rule on PSC point searching function which combines the density function of Smart MRC with algorithm. The result shows that this function could save the PSC selection time and also improvement the fail rate of PSC selection. A well-prepared inspection recipe could be done by automation tool. Therefore, the setup time on DB inspection could be minimized, also could save inspection resource as well.

In extreme ultra violate(EUV) era, the resolution is highly improved by its shorter wavelength than ArF lithography. That changes double patterning technology(DPT) or quadratic pattering technology(QPT) process by ArF to single exposure technology(SET) process by EUV. But the number of EUV photons that have same amount of energy in unit area is reduced by 10 times more than that of ArF photons, and it occurs stochastic effect like random bridge and necking defects. In other words, one EUV photon has larger energy than one ArF photon, but the unstable probability to transfer its energy to photo resist(PR) induces the lack of active energy or more of it so that results in the random defects1 . To minimize this problem, it is needed to improve normalized image log slope(NILS). Introducing curvilinear pattern is one of the techniques improves NILS and it seems that optical proximity correction(OPC) is ready for producing them. But for their high complexity, the difficulties of actual implementation on mask are remained. In the paper, we will announce the several difficulties and requirement to raise the maturity for curvilinear pattern mask fabrication.