This PDF file contains the front matter associated with SPIE Proceedings Volume 10149, including the Title Page, Copyright information, Table of Contents, Introduction (if any), and Conference Committee listing.

Transistor scaling has transitioned from wavelength scaling to multi-patterning techniques, due to the resolution limits of immersion of immersion lithography. Deposition and etch have enabled scaling in the by means of SADP and SAQP. Spacer based patterning enables extremely small linewidths, sufficient for several future generations of transistors. However, aligning layers in Z-direction, as well as aligning cut and via patterning layers, is becoming a road-block due to global and local feature variation and fidelity. This presentation will highlight the impact of deposition and etch on this feature alignment (EPE) and illustrate potential paths toward lowering EPE using material engineering.

Research and development activities related to Extreme Ultra Violet [EUV] defined patterning continue to grow for < 40 nm pitch applications. The confluence of high cost and extreme process control challenges of Self-Aligned Quad Patterning [SAQP] with continued momentum for EUV ecosystem readiness could provide cost advantages in addition to improved intra-level overlay performance relative to multiple patterning approaches. However, Line Edge Roughness [LER] and Line Width Roughness [LWR] performance of EUV defined resist images are still far from meeting technology needs or ITRS spec performance. Furthermore, extreme resist height scaling to mitigate flop over exacerbates the plasma etch trade-offs related to traditional approaches of PR smoothing, descum implementation and maintaining 2D aspect ratios of short lines or elliptical contacts concurrent with ultra-high photo resist [PR] selectivity. In this paper we will discuss sources of LER/LWR, impact of material choice, integration, and innovative plasma process techniques and describe how TEL^TM Vigus^TM CCP Etchers can enhance PR selectivity, reduce LER/LWR, and maintain 2D aspect ratio of incoming patterns. Beyond traditional process approaches this paper will show the utility of: [1] DC Superposition in enhancing EUV resist hardening and selectivity, increasing resistance to stress induced PR line wiggle caused by CFx passivation, and mitigating organic planarizer wiggle; [2] Quasi Atomic Layer Etch [Q-ALE] for ARC open eliminating the tradeoffs between selectivity, CD, and shrink ratio control; and [3] ALD+Etch FUSION technology for feature independent CD shrink and LER reduction. Applicability of these concepts back transferred to 193i based lithography is also confirmed.

In this work, we present and compare two integration approaches to enable self-alignment of the block suitable for the 5- nm technology node. The first approach is exploring the insertion of a spin-on metal-based material to memorize the first block and act as an etch stop layer in the overall integration. The second approach is evaluating the self-aligned block technology employing widely used organic materials and well-known processes. The concept and the motivation are discussed considering the effects on design and mask count as well as the impact on process complexity and EPE budget. We show the integration schemes and discuss the requirements to enable self-alignment. We present the details of materials and processes selection to allow optimal selective etches and we demonstrate the proof of concept using a 16- nm half-pitch BEOL vehicle. Finally, a study on technology insertion and cost estimation is presented.

The abstract is not available

Sidewall image transfer has become a key enabler of future design shrink. It is consisted of several process steps that multiply the number of lithography backbone patterns in a self-aligned form, shrinking pattern and pitch sizes.

The quality of the image transfer process depends on the characteristics of the sidewall pattern morphology. Rectangular Sidewalls with a flat top and vertical edges will result with symmetrical and uniform etched image. On the other hand, Facet top, bent sidewalls, sloped edges or foot, may distort the etched image and device electrical characteristics.

In this paper we present a description of the 3DSEM metrology technique used and simulation results. We demonstrate three dimensional characterization of Sidewalls pattern fabricated with different etch recipes:

Top Facet measurements vs cross section images

Spacer edge slop and oxide recess characterization

Silicon photonics is rapidly becoming the key enabler for meeting the future data speed and volume required by the Internet of Things. A stable manufacturing process is needed to deliver cost and yield expectations to the technology marketplace. We present the key challenges and technical results from both 200mm and 300mm facilities for a silicon photonics fabrication process which includes monolithic integration with CMOS. This includes waveguide patterning, optical proximity correction for photonic devices, silicon thickness uniformity and thick material patterning for passive fiber to waveguide alignment. The device and process metrics show that the transfer of the silicon photonics process from 200mm to 300mm will provide a stable high volume manufacturing platform for silicon photonics designs.

The LER and LWR of subtractively patterned Si and SiN waveguides was calculated after each step in the process. It was found for Si waveguides that adjusting the ratio of CF₄:CHF₃ during the hard mask open step produced reductions in LER of 26 and 43% from the initial lithography for isolated waveguides patterned with partial and full etches, respectively. However for final LER values of 3.0 and 2.5 nm on fully etched Si waveguides, the corresponding optical loss measurements were indistinguishable. For SiN waveguides, introduction of C4H9F to the conventional CF₄/CHF₃ measurement was able to reduce the mask height budget by a factor of 5, while reducing LER from the initial lithography by 26%.

In this paper, we report on plasma assisted thermal Atomic Layer Etching (ALE) of Al₂O₃. The surface was modified via a fluorine containing plasma without bias power. The removal was accomplished by a thermal reaction step using tin-(II) acetylacetonate Sn(acac)₂. After a few cycles, material removal stopped and growth of a Sn-containing layer was observed. Insertion of a hydrogen plasma step was found to remove the Sn layer and a continuous material removal of 0.5 Å/cycle was measured. The results show that plasma assistance can be used to realize thermal ALE of Al₂O₃. Specifically, plasma can be used both in the fluorination step and to keep the surface free from contaminations.

To meet scaling requirements, the semiconductor industry has extended 193nm immersion lithography beyond its minimum pitch limitation using multiple patterning schemes such as self-aligned double patterning, self-aligned quadruple patterning and litho-etch / litho etch iterations. Those techniques have been declined in numerous options in the last few years. Spacer on spacer pitch splitting integration has been proven to show multiple advantages compared to conventional pitch splitting approach. Reducing the number of pattern transfer steps associated with sacrificial layers resulted in significant decrease of cost and an overall simplification of the double pitch split technique.

While demonstrating attractive aspects, SAQP spacer on spacer flow brings challenges of its own. Namely, material set selections and etch chemistry development for adequate selectivities, mandrel shape and spacer shape engineering to improve edge placement error (EPE). In this paper we follow up and extend upon our previous learning and proceed into more details on the robustness of the integration in regards to final pattern transfer and full wafer critical dimension uniformity. Furthermore, since the number of intermediate steps is reduced, one will expect improved uniformity and pitch walking control. This assertion will be verified through a thorough pitch walking analysis.

Phase change material (PCM)-based memory cells have shown promise as an enabler for low power, high density memory. There is a current need to develop and improve patterning strategies to attain smaller device dimensions. In this work, two methods of patterning of PCM device structures was achieved using directed self-assembly (DSA) patterning: the formation of a high aspect ratio pore designed for atomic layer deposition (ALD) of etch damage-free PCM, and pillar formation by image reversal and plasma etch transfer into a PCM film. We show significant CD reduction (180 nm to 20 nm) of a lithographically defined hole by plasma etch shrink, DSA spin-coat and subsequent high selectivity pattern transfer. We then demonstrate structural fabrication of both DSA-defined SiN pores with ALD PCM and DSA-defined PCM pillars. Challenges to both pore and pillar fabrication are discussed.

In the lithography landscape, EUV technology recovered some credibility recently. However, its large adoption remains uncertain. Meanwhile, 193nm immersion lithography, with multiple-patterning strategies, supports the industry preference for advanced-node developments. In this landscape, lithography alternatives maintain promise for continued R&D. Massively parallel electron-beam and nano-imprint lithography techniques remain highly attractive, as they can provide noteworthy cost-of-ownership benefits. Directed self-assembly lithography shows promising resolution capabilities and appears to be an option to reduce multi-patterning strategies. Even if large amount of efforts are dedicated to overcome the lithography side issues, these solutions introduce also new challenges and opportunities for the integration schemes.

Today the IC manufacturing faces lots of problematics linked to the continuous down scaling of printed structures. Some of those issues are related to wet processing, which are often used in the IC manufacturing flow for wafer cleaning, material etching and surface preparation. In the current work we summarize the limitations for the next nodes of wet processing such as metallic contaminations, wafer charging, corrosion and pattern collapse. As a replacement, we promoted the isotropic chemical dry etching (CDE) which is supposed to fix all the above drawbacks. Etching steps of SI3N4 layers were evaluated in order to prove the interest of such technique.

The evolution of integrated components in the semiconductors industry is nowadays looking for ultra-high selective etching processes in order to etch high aspect ratio structures in complicated stacks of ultrathin layers. For ultra-high selective processes, typical plasma etching show limitations, while wet etching processes reach limitations due to capillary forces. For these reasons there is a great regain of interest today in chemical downstream etching systems (CDE), which combine the advantages of plasma and wet treatments. The absence of photons and ions allow to minimize damages and to achieve very high selectivity (in isotropic etching). In this work we investigated the parameters enabling to etch selectively the Si₃N₄ to the SiO₂ by CDE. We shown that the correlation between the gas mixture and the wafer temperature is the key to obtain the desired selectivity. In order to optimize the processing window, the mixture composition (NF₃/N₂/O₂/He) and the temperatures were screened by several DOE (Designs Of Experiments). Conditions are found in which the etching selectivity between the two silicon alloys is higher than 100, which allowed us to clean out sacrificial Si₃N₄ layers in very high aspect ratio (about 100) silicon trenches of nanometric size (60nm) without damaging the 10nm thin SiO₂ caping layer (between the Si and the Si₃N₄). This demonstrates that downstream plasma etching can perform better than wet treatments in this case.

Complimentary lithography is already being used for advanced logic patterns. The tight pitches for 1D Metal layers are expected to be created using spacer based multiple patterning ArF-i exposures and the more complex cut/block patterns are made using EUV exposures. At the same time, control requirements of CDU, pattern shift and pitch-walk are approaching sub-nanometer levels to meet edge placement error (EPE) requirements. Local variability, such as Line Edge Roughness (LER), Local CDU, and Local Placement Error (LPE), are dominant factors in the total Edge Placement error budget. In the lithography process, improving the imaging contrast when printing the core pattern has been shown to improve the local variability. In the etch process, it has been shown that the fusion of atomic level etching and deposition can also improve these local variations. Co-optimization of lithography and etch processing is expected to further improve the performance over individual optimizations alone.

To meet the scaling requirements and keep process complexity to a minimum, EUV is increasingly seen as the platform for delivering the exposures for both the grating and the cut/block patterns beyond N7. In this work, we evaluated the overlay and pattern fidelity of an EUV block printed in a negative tone resist on an ArF-i SAQP grating. High-order Overlay modeling and corrections during the exposure can reduce overlay error after development, a significant component of the total EPE. During etch, additional degrees of freedom are available to improve the pattern placement error in single layer processes.

Process control of advanced pitch nanoscale-multi-patterning techniques as described above is exceedingly complicated in a high volume manufacturing environment. Incorporating potential patterning optimizations into both design and HVM controls for the lithography process is expected to bring a combined benefit over individual optimizations. In this work we will show the EPE performance improvement for a 32nm pitch SAQP + block patterned Metal 2 layer by cooptimizing the lithography and etch processes. Recommendations for further improvements and alternative processes will be given.

Multipatterning has enabled continued scaling of chip technology at the 28nm node and beyond. Selfaligned double patterning (SADP) and self-aligned quadruple patterning (SAQP) as well as Litho- Etch/Litho-Etch (LELE) iterations are widely used in the semiconductor industry to enable patterning at sub 193 immersion lithography resolutions for layers such as FIN, Gate and critical Metal lines. Multipatterning requires the use of multiple masks which is costly and increases process complexity as well as edge placement error variation driven mostly by overlay. To mitigate the strict overlay requirements for advanced technology nodes (7nm and below), a self-aligned blocking integration is desirable. This integration trades off the overlay requirement for an etch selectivity requirement and enables the cut mask overlay tolerance to be relaxed from half pitch to three times half pitch. Selfalignement has become the latest trend to enable scaling and self-aligned integrations are being pursued and investigated for various critical layers such as contact, via, metal patterning.

In this paper we propose and demonstrate a low cost flexible self-aligned blocking strategy for critical metal layer patterning for 7nm and beyond from mask assembly to low –K dielectric etch. The integration is based on a 40nm pitch SADP flow with 2 cut masks compatible with either cut or block integration and employs dielectric films widely used in the back end of the line. As a consequence this approach is compatible with traditional etch, deposition and cleans tools that are optimized for dielectric etches. We will review the critical steps and selectivities required to enable this integration along with bench-marking of each integration option (cut vs. block).

Scaling beyond the 7nm technology node demands significant control over the variability down to a few angstroms, in order to achieve reasonable yield. For example, to meet the current scaling targets it is highly desirable to achieve sub 30nm pitch line/space features at back-end of the line (BEOL) or front end of line (FEOL); uniform and precise contact/hole patterning at middle of line (MOL). One of the quintessential requirements for such precise and possibly self-aligned patterning strategies is superior etch selectivity between the target films while other masks/films are exposed. The need to achieve high etch selectivity becomes more evident for unit process development at MOL and BEOL, as a result of low density films choices (compared to FEOL film choices) due to lower temperature budget. Low etch selectivity with conventional plasma and wet chemical etch techniques, causes significant gouging (un-intended etching of etch stop layer, as shown in Fig 1), high line edge roughness (LER)/line width roughness (LWR), non-uniformity, etc. In certain circumstances this may lead to added downstream process stochastics. Furthermore, conventional plasma etches may also have the added disadvantage of plasma VUV damage and corner rounding (Fig. 1). Finally, the above mentioned factors can potentially compromise edge placement error (EPE) and/or yield.

Therefore a process flow enabled with extremely high selective etches inherent to film properties and/or etch chemistries is a significant advantage. To improve this etch selectivity for certain etch steps during a process flow, we have to implement alternate highly selective, plasma free techniques in conjunction with conventional plasma etches (Fig 2.). In this article, we will present our plasma free, chemical gas phase etch technique using chemistries that have high selectivity towards a spectrum of films owing to the reaction mechanism ( as shown Fig 1). Gas phase etches also help eliminate plasma damage to the features during the etch process. Herein we will also demonstrate a test case on how a combination or plasma assisted and plasma free etch techniques has the potential to improve process performance of a 193nm immersion based self aligned quandruple patterning (SAQP) for BEOL compliant films (an example shown in Fig 2). In addition, we will also present on the application of gas etches for (1) profile improvement, (2) selective mandrel pull (3) critical dimension trim of mandrels, with an analysis of advantages over conventional techniques in terms of LER and EPE.

Increasingly, advanced process nodes such as 7nm (N7) are fundamentally 3D and require stringent control of critical dimensions over high aspect ratio features. Process integration in these nodes requires a deep understanding of complex physical mechanisms to control critical dimensions from lithography through final etch. Polysilicon gate etch processes are critical steps in several device architectures for advanced nodes that rely on self-aligned patterning approaches to gate definition. These processes are required to meet several key metrics: (a) vertical etch profiles over high aspect ratios; (b) clean gate sidewalls free of etch process residue; (c) minimal erosion of liner oxide films protecting key architectural elements such as fins; and (e) residue free corners at gate interfaces with critical device elements. In this study, we explore how hybrid modeling approaches can be used to model a multi-step finFET polysilicon gate etch process. Initial parts of the patterning process through hardmask assembly are modeled using process emulation. Important aspects of gate definition are then modeled using a particle Monte Carlo (PMC) feature scale model that incorporates surface chemical reactions.¹ When necessary, species and energy flux inputs to the PMC model are derived from simulations of the etch chamber. The modeled polysilicon gate etch process consists of several steps including a hard mask breakthrough step (BT), main feature etch steps (ME), and over-etch steps (OE) that control gate profiles at the gate fin interface. An additional constraint on this etch flow is that fin spacer oxides are left intact after final profile tuning steps. A natural optimization required from these processes is to maximize vertical gate profiles while minimizing erosion of fin spacer films.²

This paper reviews some recent activity at the James Watt Nanofabrication Centre in the University of Glasgow in the area of plasma processing for energy efficient compound semiconductor-based transistors. Atomic layer etching suitable for controllable recess etching in GaN power transistors will be discussed. In addition, plasma based surface passivation techniques will be reviewed for a variety of compound semiconductor materials ((100) and (110) oriented InGaAs and InGaSb).

The infrared absorption of SF₆ gas is of narrowband and peaks at 10.6μm. This narrow band absorption posts a stringent requirement on the corresponding sensors as they need to collect enough signal from this limited spectral range to maintain a high sensitivity. Resonator-Quantum Well Infrared Photo detectors (R-QWIPs) are the next generation of QWIP detectors that use resonances to increase the quantum efficiency (QE) for more efficient signal collection. Since the resonant approach is applicable to narrowband as well as broadband, it is particularly suitable for this application. We designed and fabricated R-QWIPs for SF₆ gas detection. To achieve the expected performance, the detector geometry must be produced according to precise specifications. In particular, the height of the diffractive elements (DE) and the thickness of the active resonator must be uniform, and accurately realized to within 0.05 μm. additionally, the substrates of the detectors must be removed totally to prevent the escape of unabsorbed light in the detectors. To achieve these specifications, two optimized inductively coupled plasma (ICP) etching processes are developed. Due to submicron detector feature sizes and overlay tolerance, we use an ASML stepper instead of a contact mask aligner to pattern wafers. Using these etching techniques and tool, we have fabricated FPAs with 30 μm pixel pitch and 320x256 format. The initial test results showed promising results.

There is a growing interest in new spin on metal oxide hard mask materials for advanced patterning solutions both in BEOL and FEOL processing. Understanding how these materials respond to plasma conditions may create a competitive advantage. In this study patterning development was done for two challenging FEOL applications where the traditional Si based films were replaced by EMD spin on metal oxides, which acted as highly selective hard masks. The biggest advantage of metal oxide hard masks for advanced patterning lays in the process window improvement at lower or similar cost compared to other existing solutions.

Block copolymers (BCPs) are consisted of at least two types of monomers which have covalent bonding. One of the widely investigated BCPs is polystyrene-block-polydimethylsiloxane (PS-b-PDMS), which is used as an alternative patterning method for various deep nanoscale devices due to its high Flory-Huggins interaction parameter (χ), such as optical devices and transistors, replacing conventional photolithography. As an alternate or supplementary nextgeneration lithography technology to extreme ultraviolet lithography (EUVL), BCP lithography utilizing the DSA of BCP has been actively studied. However, the nanoscale BCP mask material is easily damaged by the plasma and has a very low etch selectivity over bottom semiconductor materials, because it is composed of polymeric materials even though it contains Si in PDMS. In this study, an amorphous carbon layer (ACL) was inserted as a hardmask material between BCP and materials to be patterned, and, by using O₂ plasmas, the characteristics of dry etching of ACL for high aspect ratio (HAR) using a 10 nm PDMS pattern were investigated. The results showed that, by using a PS-b-PDMS pattern with an aspect ratio of 0.3~0.9:1, a HAR PDMS/ACL double layer mask with an aspect ratio of ~10:1 could be fabricated. In addition, by the optimization of the plasma etch process, ACL masks with excellent sidewall roughness (SWR,1.35 nm) and sidewall angle (SWA, 87.9˚) could be fabricated.

Dimension shrinkage has been a major driving force in the development of integrated circuit processing over a number of decades. The Self-Aligned Quadruple Patterning (SAQP) technique is widely adapted for sub-10nm node in order to achieve the desired feature dimensions. This technique provides theoretical feasibility of multiple pitch-halving from 193nm immersion lithography by using various pattern transferring steps. The major concept of this approach is to a create spacer defined self-aligned pattern by using single lithography print. By repeating the process steps, double, quadruple, or octuple are possible to be achieved theoretically. In these small architectures, line roughness control becomes extremely important since it may contribute to a significant portion of process and device performance variations. In addition, the complexity of SAQP in terms of processing flow makes the roughness improvement indirective and ineffective. It is necessary to discover a new approach in order to improve the roughness in the current SAQP technique.

In this presentation, we demonstrate a novel method to improve line roughness performances on 30nm pitch SAQP flow. We discover that the line roughness performance is strongly related to stress management. By selecting different stress level of film to be deposited onto the substrate, we can manipulate the roughness performance in line and space patterns. In addition, the impact of curvature change by applied film stress to SAQP line roughness performance is also studied. No significant correlation is found between wafer curvature and line roughness performance. We will discuss in details the step-by-step physical performances for each processing step in terms of critical dimension (CD)/ critical dimension uniformity (CDU)/line width roughness (LWR)/line edge roughness (LER). Finally, we summarize the process needed to reach the full wafer performance targets of LWR/LER in 1.07nm/1.13nm on 30nm pitch line and space pattern.

Next generation semiconductor technologies like high density memory storage require precise 2D and 3D nanopatterns. Plasma etching processes are essential to achieving the nanoscale precision required for these structures. Current plasma process development methods rely primarily on iterative trial and error or factorial design of experiment (DOE) to define the plasma process space. Here we evaluate the efficacy of the software tool Recipe Optimization for Deposition and Etching (RODEo) against standard industry methods at determining the process parameters of a high density O₂ plasma system with three case studies. In the first case study, we demonstrate that RODEo is able to predict etch rates more accurately than a regression model based on a full factorial design while using 40% fewer experiments. In the second case study, we demonstrate that RODEo performs significantly better than a full factorial DOE at identifying optimal process conditions to maximize anisotropy. In the third case study we experimentally show how RODEo maximizes etch rates while using half the experiments of a full factorial DOE method. With enhanced process predictions and more accurate maps of the process space, RODEo reduces the number of experiments required to develop and optimize plasma processes.

As CMOS technology reaches 14nm node and beyond, one of the key challenges of the extension of 193nm immersion lithography is how to control the line edge and width roughness (LER/LWR). For Self-aligned Multiple Patterning (SaMP), LER becomes larger while LWR becomes smaller as the process proceeds^[1]. It means plasma etch process becomes more and more dominant for LER reduction. In this work, we mainly focus on the core etch solution including an extra plasma coating process introduced before the bottom anti reflective coating (BARC) open step, and an extra plasma cure process applied right after BARC-open step. Firstly, we leveraged the optimal design experiment (ODE) to investigate the impact of plasma coating step on LER and identified the optimal condition. ODE is an appropriate method for the screening experiments of non-linear parameters in dynamic process models, especially for high-cost-intensive industry ^[2]. Finally, we obtained the proper plasma coating treatment condition that has been proven to achieve 32% LER improvement compared with standard process. Furthermore, the plasma cure scheme has been also optimized with ODE method to cover the LWR degradation induced by plasma coating treatment.

Following Moore’s law, integrated circuit requires scaling gate length to 14nm and beyond. To enable such gate-length scaling, finFETs have widely replaced planar metal-oxide-semiconductor field-effect transistors (MOSFETs) due to its special 3D structure could provide larger effective channel width and better short channel controllability. However, Fin critical dimension (CD) and profile variation between dense and ISO fin in a conventional etch process can introduce additional device degradation. Therefore, rigorous process loading control in reactive ion etch (RIE) becomes more critical. This paper mainly focused on self-aligned double patterning mandrel etch and fin etch by using advanced pulsed plasma to deliver a well-loading fin.

In this work, we present an attractive and novel fabrication technique that can produce highly-controlled silicon-based nanostructures in wafer-scale by a seldom used material in IC fabrication, amorphous silicon (α-Si), as an etch mask. The α-Si mask pattern is precisely transferred into the underlying SiO₂ substrate material with a high fidelity by a novel top-down fabrication. It is the first time for α-Si film used as an etch mask to fabricate various Si-based nanostructures. It is observed that the α-Si mask can significantly reduce the pattern edge roughness and achieve highly uniform and smooth sidewalls. SiO₂ nanostructures directly fabricated can be served as nanotemplates to transfer into the underlying substrates such as silicon, germanium, transistor gate or other dielectric materials to form electrically functional nanostructures and devices. Several typical Si-based nanostructures, such as nanoline, nanofin and transistor gate patterning, have been fabricated successfully using the simple α-Si material combining with electron beam lithography. Our results demonstrate that the Si-based nanostructures as small as sub-20 nm may be achievable. More significantly, the novel approach is a potentially universal method that is fully compatible with the current existing Si-based CMOS technologies.